Table of contents for VHDL : programming by example / Douglas L. Perry.

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 Chapter 1: Introduction to VHDL
 Chapter 2: Behavioral Modeling
 Chapter 3: Sequential Processing
 Chapter 4: Data Types
 Chapter 5: Subprograms and Packages
 Chapter 6: Predefined Attributes
 Chapter 7: Configurations
 Chapter 8: Advanced Topics
 Chapter 9: Synthesis
 Chapter 10: VHDL Systems
 Chapter 11: High Level Design Flow
 Chapter 12: Top-Level System Design
 Chapter 13: CPU: Synthesis Description
 Chapter 14: CPU: RTL Simulation
 Chapter 15: CPU Design: Synthesis Results
 Chapter 16: Place and Route
 Chapter 17: CPU: VITAL Simulation
 Chapter 18: At Speed Debugging Techniques
 Appendix A: Standard Logic Package
 Appendix B: VHDL Reference Tables
 Appendix C: Reading VHDL BNF
 Appendix D: VHDL93 Updates
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