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1. Taxonomy of Leakage: Sources, Impact, and Solutions 1.1 Introduction 1 1.2 Sources 3 1.3 Impact 11 1.4 Solutions 13 References 18 2. Leakage Dependence on Input Vector SIVA NARENDRA, YIBIN YE, SHEKAR BORKAR, VIVEK DE, AND ANANTHA CHANDRAKASAN 2.1 Introduction 21 2.2 Stack Effect 23 2.3 Leakage Reduction using Natural Stacks 30 2.4 Leakage Reduction using Forced Stacks 35 2.5 Summary 38 References 39 3. Power Gating and Dynamic Voltage Scaling BENTON CALHOUN, JAMES KAO, AND ANANTHA CHANDRAKASAN 3.1 Introduction 41 3.2 Power Gating 41 3.3 Dynamic Voltage Scaling 64 3.4 Summary 73 References 73 4. Methodologies for Power Gating KIMIYOSHI USAMI AND TAKAYASU SAKURAI 4.1 Introduction 77 4.2 Power Gating Methodologies for Real Designs 79 4.3 Future Directions of Power Gating 90 4.4 Summary 102 References 103 5. Body Biasing TADAHIRO KURODA AND TAKAYASU SAKURAI 5.1 Introduction 105 5.2 Reverse Body Bias 107 5.3 Forward Body Bias 126 5.4 Future Directions 137 References 139 6. Process Variation and Adaptive Design SIVA NARENDRA, JAMES TSCHANZ, JAMES KAO, SHEKAR BORKAR, ANANTHA CHANDRAKASAN, AND VIVEK DE 6.1 Introduction 141 6.2 Bi-directional Adaptive Body Bias 143 6.3 Body Bias Circuit Impedance 150 6.4 Adaptive Supply Voltage and Adaptive Body Bias 156 References 162 7. Memory Leakage Reduction TAKAYUKI KAWAHARA AND KIYOO ITOH 7.1 Introduction 163 7.2 Leakage in RAMs 164 7.3 Leakage Sources and Reduction in RAMs 168 7.4 Various Leakage Reduction Schemes 171 7.5 Gate-Source Reverse Biasing Schemes 175 7.6 Applications to RAM Cells 180 7.7 Applications to Peripheral Circuits 186 7.8 Future Prospects 195 7.9 Conclusion 196 References 196 8. Active Leakage Reduction and Multi-Performance Devices SIVA NARENDRA, JAMES TSCHANZ, SHEKAR BORKAR, AND VIVEK DE 8.1 Introduction 201 8.2 Standby Techniques for Active Leakage Reduction 202 8.3 Multi-performance Devices 208 References 209 9. Impact of Leakage Power and Variation on Testing ALI KESHAVARZI AND KAUSHIK ROY 9.1 Introduction 211 9.2 Background 212 9.3 Leakage vs. Frequency Characterization 214 9.4 Multiple-Parameter Testing 216 9.5 Sensitivity Gain with RBB and Temperature 218 9.6 Leakage versus Temperature Two-Parameter Test Solution 227 9.7 Discussions and Test Applications 229 9.8 Conclusion 232 References 232 10. Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors MASAYUKI MIYAZAKI, HIROYUKI MIZUNO, AND TAKAYUKI KAWAHARA 10.1 Leakage Reduction Using Body Bias in a RISC 235 Microprocessor 10.2 Leakage Reduction in Application Processor in 3G 240 Cellular Phone 10.3 Leakage Reduction in SRAM module 249 References 255 11. Case Study: Leakage Reduction in the Intel Xscale Microprocessor LAWRENCE CLARK 11.1 Introduction 257 11.2 Circuit Configuration and Operation 261 11.3 Regulator Design 267 11.4 Time-Division Multiplexed Operation 273 11.5 SOC Design Issues and Future Trends 276 11.6 Conclusion 278 12. Transistor Design to Reduce Leakage SAGAR SUTHRAM, SIVA NARENDRA, AND SCOTT THOMPSON 12.1 Introduction 281 12.2 Sub-threshold Leakage in Nanoscale Planar Si 282 MOSFETs 12.3 SiON Dielectrics to Reduce Gate to Channel Direct 286 Tunneling Current 12.4 Offset Spacers to Reduce Edge Direct Tunneling 286 Current 12.5 Compensation Implants to Reduce Junction Leakage 287 12.6 Source/Drain Extension Grading to Reduce Gate 289 Induced Drain Leakage (GIDL) 12.7 Future Solutions 291 12.8 Summary 298 References 298