## Table of contents for Fundamentals of digital logic with VHDL design / Stephen Brown, Zvonko Vranesic.

Bibliographic record and links to related information available from the Library of Congress catalog.

Note: Contents data are machine generated based on pre-publication provided by the publisher. Contents may have variations from the printed book or be incomplete or contain other coding.

```Contents
C h a p t e r 1
Design Concepts 1
1.1 Digital Hardware 2
1.1.1 Standard Chips 4
1.1.2 Programmable Logic Devices 4
1.1.3 Custom-Designed Chips 5
1.2 The Design Process 6
1.3 Design of Digital Hardware 8
1.3.1 Basic Design Loop 8
1.3.2 Structure of a Computer 9
1.3.3 Design of a Digital Hardware Unit 12
1.5 Theory and Practice 16 References 17
C h a p t e r 2
Introduction to Logic Circuits 19
2.1 Variables and Functions 20
2.2 Inversion 23
2.3 Truth Tables 24
2.4 Logic Gates and Networks 25
2.4.1 Analysis of a Logic Network 27
2.5 Boolean Algebra 29
2.5.1 The Venn Diagram 33
2.5.2 Notation and Terminology 35
2.5.3 Precedence of Operations 37
2.6 Synthesis Using AND, OR, and NOT Gates 37
2.6.1 Sum-of-Products and Product-of-Sums Forms 39
2.7 NAND and NOR Logic Networks 45
2.8 Design Examples 50
2.8.1 Three-Way Light Control 50
2.8.2 Multiplexer Circuit 51
2.9 Introduction to CAD Tools 54
2.9.1 Design Entry 54
2.9.2 Synthesis 56
2.9.3 Functional Simulation 57
2.9.4 Physical Design 57
2.9.5 Timing Simulation 57
2.9.6 Chip Con?guration 58
2.10 Introduction to VHDL 58
2.10.1 Representation of Digital Signals in VHDL 60
2.10.2 Writing Simple VHDL Code 60
2.10.3 How Not to Write VHDL Code 62
2.11 Concluding Remarks 63
2.12 Examples of Solved Problems 64 Problems 67 References 72
C h a p t e r 3
Implementation Technology 73
3.1 Transistor Switches 75
3.2 NMOS Logic Gates 78
3.3 CMOS Logic Gates 81
3.3.1 Speed of Logic Gate Circuits 87
3.4 Negative Logic System 87
3.5 Standard Chips 91
3.5.1 7400-Series Standard Chips 91
3.6 Programmable Logic Devices 94
3.6.1 Programmable Logic Array (PLA) 94
3.6.2 Programmable Array Logic (PAL) 97
3.6.3 Programming of PLAs and PALs 99
3.6.4 Complex Programmable Logic Devices (CPLDs) 101
3.6.5 Field-Programmable Gate Arrays 105
3.6.6 Using CAD Tools to Implement Circuits in CPLDs and FPGAs 110
3.6.7 Application of CPLDs and FPGAs 110
3.7 Custom Chips, Standard Cells, and Gate Arrays 110
3.8 Practical Aspects 114
3.8.1 MOSFET Fabrication and Behavior 114
3.8.2 MOSFET On-Resistance 117
3.8.3 Voltage Levels in Logic Gates 118
3.8.4 Noise Margin 119
3.8.5 Dynamic Operation of Logic Gates 121
3.8.6 Power Dissipation in Logic Gates 124
3.8.7 Passing 1s and 0s Through Transistor Switches 126
3.8.8 Fan-in and Fan-out in Logic Gates 128
3.9 Transmission Gates 134
3.9.1 Exclusive-OR Gates 135
3.9.2 Multiplexer Circuit 136
3.10 Implementation Details for SPLDs, CPLDs, and FPGAs 136
3.10.1 Implementation in FPGAs 142
3.11 Concluding Remarks 145
3.12 Examples of Solved Problems 145 Problems 153 References 162
C h a p t e r 4
Optimized Implementation of Logic Functions 163
4.1 Karnaugh Map 164
4.2 Strategy for Minimization 172
4.2.1 Terminology 173
4.2.2 Minimization Procedure 175
4.3 Minimization of Product-of-Sums Forms 178
4.4 Incompletely Speci?ed Functions 180
4.5 Multiple-Output Circuits 182
4.6 Multilevel Synthesis 185
4.6.1 Factoring 186
4.6.2 Functional Decomposition 190
4.6.3 Multilevel NAND and NOR Circuits 195
4.7 Analysis of Multilevel Circuits 196
4.8 Cubical Representation 203
4.8.1 Cubes and Hypercubes 203
4.9 A Tabular Method for Minimization 207
4.9.1 Generation of Prime Implicants 208
4.9.2 Determination of a Minimum Cover 209
4.9.3 Summary of the Tabular Method 215
4.10 A Cubical Technique for Minimization 216
4.10.1 Determination of Essential Prime Implicants 218
4.10.2 Complete Procedure for Finding a Minimal Cover 220
4.11 Practical Considerations 223
4.12 Examples of Circuits Synthesized from VHDL Code 224
4.13 Concluding Remarks 228
4.14 Examples of Solved Problems 229 Problems 237 References 242
C h a p t e r 5
Number Representation and Arithmetic Circuits 245
5.1 Positional Number Representation 246
5.1.1 Unsigned Integers 246
5.1.2 Conversion between Decimal and Binary Systems 247
5.1.3 Octal and Hexadecimal Representations 248
5.2 Addition of Unsigned Numbers 250
5.2.3 Design Example 256
5.3 Signed Numbers 256
5.3.1 Negative Numbers 256
5.3.3 Adder and Subtractor Unit 264
5.3.5 Arithmetic Over?ow 269
5.3.6 Performance Issues 270
5.5 Design of Arithmetic Circuits Using CAD Tools 278
5.5.1 Design of Arithmetic Circuits Using Schematic Capture 278
5.5.2 Design of Arithmetic Circuits Using VHDL 281
5.5.3 Representation of Numbers in VHDL Code 284
5.5.4 Arithmetic Assignment Statements 285
5.6 Multiplication 289
5.6.1 Array Multiplier for Unsigned Numbers 291
5.6.2 Multiplication of Signed Numbers 292
5.7 Other Number Representations 293
5.7.1 Fixed-Point Numbers 293
5.7.2 Floating-Point Numbers 295
5.7.3 Binary-Coded Decimal Representation 297
5.8 ASCII Character Code 301
5.9 Examples of Solved Problems 304 Problems 310 References 314
C h a p t e r 6
Combinational-Circuit Building Blocks 315
6.1 Multiplexers 316
6.1.1 Synthesis of Logic Functions Using Multiplexers 321
6.1.2 Multiplexer Synthesis Using Shannon?s Expansion 324
6.2 Decoders 329
6.2.1 Demultiplexers 333
6.3 Encoders 335
6.3.1 Binary Encoders 335
6.3.2 Priority Encoders 336
6.4 Code Converters 337
6.5 Arithmetic Comparison Circuits 338
6.6 VHDL for Combinational Circuits 339
6.6.1 Assignment Statements 339
6.6.2 Selected Signal Assignment 340
6.6.2 Selected Signal Assignment 340
6.6.3 Conditional Signal Assignment 344
6.6.4 Generate Statements 348
6.6.5 Concurrent and Sequential Assignment Statements 350
6.6.6 Process Statement 350
6.6.7 Case Statement 356
6.6.8 VHDL Operators 359
6.7 Concluding Remarks 363
6.8 Examples of Solved Problems 364 Problems 372 References 377
C h a p t e r 7
Flip-Flops, Registers, Counters, and a Simple Processor 379
7.1 Basic Latch 381
7.2 Gated SR Latch 383
7.2.1 Gated SR Latch with NAND Gates 385
7.3 Gated D Latch 386
7.3.1 Effects of Propagation Delays 388
7.4 Master-Slave and Edge-Triggered D Flip-Flops 389
7.4.1 Master-Slave D Flip-Flop 389
7.4.2 Edge-Triggered D Flip-Flop 389
7.4.3 D Flip-Flops with Clear and Preset 393
7.5 T Flip-Flop 394
7.5.1 Con?gurable Flip-Flops 397
7.6 JK Flip-Flop 397
7.7 Summary of Terminology 398
7.8 Registers 399
7.8.1 Shift Register 399
7.8.2 Parallel-Access Shift Register 400
7.9 Counters 400
7.9.1 Asynchronous Counters 401
7.9.2 Synchronous Counters 404
7.9.3 Counters with Parallel Load 408
7.10 Reset Synchronization 408
7.11 Other Types of Counters 412
7.11.1 BCD Counter 412
7.11.2 Ring Counter 413
7.11.3 Johnson Counter 415
7.11.4 Remarks on Counter Design 415
7.12 Using Storage Elements with CAD Tools 416
7.12.1 Including Storage Elements in Schematics 416
7.12.2 Using VHDL Constructs for Storage Elements 417
7.13 Using Registers and Counters with CAD Tools 423
7.13.1 Including Registers and Counters in Schematics 423
7.13.2 Registers and Counters in VHDL Code 426
7.13.3 Using VHDL Sequential Statements for Registers and Counters 427
7.14 Design Examples 435
7.14.1 Bus Structure 435
7.14.2 Simple Processor 449
7.14.3 Reaction Timer 460
7.14.4 Register Transfer Level (RTL) Code 466
7.15 Concluding Remarks 466
7.16 Examples of Solved Problems 467 Problems 471 References 477
C h a p t e r 8
Synchronous Sequential Circuits 479
8.1 Basic Design Steps 481
8.1.1 State Diagram 481
8.1.2 State Table 483
8.1.3 State Assignment 483
8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions 485
8.1.5 Timing Diagram 486
8.1.6 Summary of Design Steps 488
8.2 State-Assignment Problem 491
8.2.1 One-Hot Encoding 494
8.8.2 Minimizing the Output Delays for an FSM 550
8.8.3 Summary 551
8.3 Mealy State Model 496
8.4 Design of Finite State Machines Using CAD Tools 501
8.4.1 VHDL Code for Moore-Type FSMs 502
8.4.2 Synthesis of VHDL Code 504
8.4.3 Simulating and Testing the Circuit 506
8.4.4 An Alternative Style of VHDL Code 507
8.4.5 Summary of Design Steps When Using CAD Tools 507
8.4.6 Specifying the State Assignment in VHDL Code 509
8.4.7 Speci?cation of Mealy FSMs Using VHDL 511
8.5.1 Mealy-Type FSM for Serial Adder 514
8.5.2 Moore-Type FSM for Serial Adder 516
8.5.3 VHDL Code for the Serial Adder 518
8.6 State Minimization 522
8.6.1 Partitioning Minimization Procedure 524
8.6.2 Incompletely Speci?ed FSMs 531
8.7 Design of a Counter Using the Sequential Circuit Approach 533
8.7.1 State Diagram and State Table for a Modulo-8 Counter 533
8.7.2 State Assignment 534
8.7.3 Implementation Using D-Type Flip-Flops 535
8.7.4 Implementation Using JK-Type Flip-Flops 536
8.7.5 Example?A Different Counter 541
8.8 FSM as an Arbiter Circuit 543
8.8.1 Implementation of the Arbiter Circuit 547
8.9 Analysis of Synchronous Sequential Circuits 551
8.10 Algorithmic State Machine (ASM) Charts 555
8.11 Formal Model for Sequential Circuits 559
8.12 Concluding Remarks 560
8.13 Examples of Solved Problems 561 Problems 570 References 574

C h a p t e r 9
Asynchronous Sequential Circuits 577
9.1 Asynchronous Behavior 578
9.2 Analysis of Asynchronous Circuits 582
9.3 Synthesis of Asynchronous Circuits 590
9.4 State Reduction 603
9.5 State Assignment 618
9.5.1 Transition Diagram 621
9.5.2 Exploiting Unspeci?ed Next-State Entries 624
9.5.3 State Assignment Using Additional State Variables 628
9.5.4 One-Hot State Assignment 633
9.6 Hazards 634
9.6.1 Static Hazards 635
9.6.2 Dynamic Hazards 639
9.6.3 Signi?cance of Hazards 640
9.7 A Complete Design Example 642
9.7.1 The Vending-Machine Controller 642
9.8 Concluding Remarks 647
9.9 Examples of Solved Problems 649 Problems 657 References 661
C h a p t e r 10
Digital System Design 663
10.1 Building Block Circuits 664
10.1.1 Flip-Flops and Registers with Enable Inputs 664
10.1.2 Shift Registers with Enable Inputs 666
10.1.3 Static Random Access Memory (SRAM) 668
10.1.4 SRAM Blocks in PLDs 673
10.2 Design Examples 673
10.2.1 A Bit-Counting Circuit 673
10.2.2 ASM Chart Implied Timing Information 675
10.2.4 Divider 686
10.2.5 Arithmetic Mean 696
10.2.6 Sort Operation 702
10.3 Clock Synchronization 713
10.3.1 Clock Skew 713
10.3.2 Flip-Flop Timing Parameters 714
10.3.3 Asynchronous Inputs to Flip-Flops 717
10.3.4 Switch Debouncing 718
10.4 Concluding Remarks 718 Problems 720 References 724
C h a p t e r 11
Testing of Logic Circuits 725
11.1 Fault Model 726
11.1.1 Stuck-at Model 726
11.1.2 Single and Multiple Faults 727
11.1.3 CMOS Circuits 727
11.2 Complexity of a Test Set 727
11.3 Path Sensitizing 729
11.3.1 Detection of a Speci?c Fault 731
11.4 Circuits with Tree Structure 733
11.5 Random Tests 734
11.6 Testing of Sequential Circuits 737
11.6.1 Design for Testability 737
11.7 Built-in Self-Test 741
11.7.1 Built-in Logic Block Observer 745
11.7.2 Signature Analysis 747
11.7.3 Boundary Scan 748
11.8 Printed Circuit Boards 748
11.8.1 Testing of PCBs 750
11.8.2 Instrumentation 751
11.9 Concluding Remarks 752 Problems 752 References 755
C h a p t e r 12
Computer Aided Design Tools 757
12.1 Synthesis 758
12.1.1 Netlist Generation 758
12.1.2 Gate Optimization 758
12.1.3 Technology Mapping 760
12.2 Physical Design 764
12.2.1 Placement 767
12.2.2 Routing 768
12.2.3 Static Timing Analysis 769
12.3 Concluding Remarks 771 References 771
A p p e n d i x A
VHDL Reference 773
A.1 Documentation in VHDL Code 774
A.2 Data Objects 774
A.2.1 Data Object Names 774
A.2.2 Data Object Values and Numbers 774
A.2.3 SIGNAL Data Objects 775
A.2.4 BIT and BIT_VECTOR Types 775
A.2.5 STD_LOGIC and STD_LOGIC_VECTOR Types 776
A.2.6 STD_ULOGIC Type 776
A.2.7 SIGNED and UNSIGNED Types 777
A.2.8 INTEGER Type 778
A.2.9 BOOLEAN Type 778
A.2.10 ENUMERATION Type 778
A.2.11 CONSTANT Data Objects 779
A.2.12 VARIABLE Data Objects 779
A.2.13 Type Conversion 779
A.2.14 Arrays 780
A.3 Operators 781
A.4 VHDL Design Entity 781
A.4.1 ENTITY Declaration 782
A.4.2 Architecture 782
A.5 Package 784
A.6 Using Subcircuits 785
A.6.1 Declaring a COMPONENT in a Package 787
A.7 Concurrent Assignment Statements 788
A.7.1 Simple Signal Assignment 789
A.7.2 Assigning Signal Values Using OTHERS 790
A.7.3 Selected Signal Assignment 791
A.7.4 Conditional Signal Assignment 792
A.7.5 GENERATE Statement 793
A.8 De?ning an Entity with GENERICs 793
A.9 Sequential Assignment Statements 794
A.9.1 PROCESS Statement 794
A.9.2 IF Statement 796
A.9.3 CASE Statement 796
A.9.4 Loop Statements 797
A.9.5 Using a Process for a Combinational Circuit 797
A.9.6 Statement Ordering 799
A.9.7 Using a VARIABLE in a PROCESS 800
A.10 Sequential Circuits 805
A.10.1 A Gated D Latch 805
A.10.2 D Flip-Flop 806
A.10.3 Using a WAIT UNTIL Statement 807
A.10.4 A Flip-Flop with Asynchronous Reset 808
A.10.5 Synchronous Reset 808
A.10.6 Registers 808
A.10.7 Shift Registers 811
A.10.8 Counters 813
A.10.9 Using Subcircuits with GENERIC Parameters 813
A.10.10 A Moore-Type Finite State Machine 816
A.10.11 A Mealy-Type Finite State Machine 818
A.11 Common Errors in VHDL Code 821
A.12 Concluding Remarks 824 References 825
A p p e n d i x B
Tutorial 2?Implementing Circuits in Altera Devices 859
C.1 Implementing a Circuit in a MAX 7000 CPLD 859
C.1.1 Selecting a Chip 860
C.1.2 Compiling the Project 861
C.1.3 Performing Timing Simulation 862
C.1.4 Using the Floorplan Editor 863
C.2 Implementing a Circuit in a Cyclone FPGA 864
C.3 Implementing an Adder using Quartus II 866
C.3.1 The Ripple-Carry Adder Code 867
C.3.2 Simulating the Circuit 868
C.3.3 Timing Simulation 871
C.3.4 Implementation in a CPLD Chip 874
C.4 Using an LPM Module 876
C.5 Design of a Finite State Machine 881
C.5.1 Implementation in a CPLD 882
C.5.2 Implementation in an FPGA 886
C.6 Concluding Remarks 887
A p p e n d i x D
Tutorial 1?Using Quartus II CAD Software 827
B.1 Introduction 827
B.1.1 Getting Started 828
B.2 Starting a New Project 830
B.3 Design Entry Using Schematic Capture 832
B.3.1 Using the Block Editor 832
B.3.2 Synthesizing a Circuit from the Schematic 840
B.3.3 Simulating the Designed Circuit 842
B.4 Design Entry Using VHDL 846
B.4.1 Create Another Project 848
B.4.2 Using the Text Editor 848
B.4.3 Synthesizing a Circuit from the VHDL Code 850
B.4.4 Performing Functional Simulation 850
B.4.5 Using Quartus II to Debug VHDL Code 850
B.5 Mixing Design-Entry Methods 851
B.5.1 Using Schematic Entry at the Top Level 851
B.5.2 Using VHDL at the Top Level 854
B.6 Quartus II Windows 856
B.7 Concluding Remarks 858
A p p e n d i x C
Tutorial 3?Physical Implementation in a PLD 889
D.1 Making Pin Assignments 889
D.1.1 Examining Pin Assignments with the Floorplan Editor 892
D.1.2 Recompiling the Project with Pin Assignments 892
D.1.3 Changing Pin Assignments by using the Floorplan Editor 894
D.3 Concluding Remarks 897
A p p e n d i x E
Commercial Devices 899
E.1 Simple PLDs 899
E.1.1 The 22V10 PAL Device 899
E.2 Complex PLDs 901 E.2.1 Altera MAX 7000 902
E.3 Field-Programmable Gate Arrays 904
E.3.1 Altera FLEX 10K 904
E.3.2 Xilinx XC4000 907
E.3.3 Altera APEX 20K 909
E.3.4 Altera Stratix 909
E.3.5 Altera Cyclone 911
E.3.6 Altera Stratix II 911
E.3.7 Xilinx Virtex 912
E.3.8 Xilinx Virtex-II and Virtex-II Pro 912
E.3.9 Xilinx Spartan-3 913
E.4 Transistor-Transistor Logic 914
E.4.1 TTL Circuit Families 914 References 916