Table of contents for The designer's guide to VHDL / Peter J. Ashenden.

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Contents
Preface	xvii
1	Fundamental Concepts	1
1.1	Modeling Digital Systems ?1
1.2	Domains and Levels of Modeling?3
1.2.1	Modeling Example?4
1.3	Modeling Languages?8
1.4	VHDL Modeling Concepts?8
1.4.1	Elements of Behavior?9
1.4.2	Elements of Structure?11
1.4.3	Mixed Structural and Behavioral Models?13
1.4.4	Test Benches?14
1.4.5	Analysis, Elaboration and Execution?15
1.5	Learning a New Language: Lexical Elements and Syntax?18
1.5.1	Lexical Elements?19
Comments?19
Identifiers?20
Reserved Words?22
Special Symbols?23
Numbers?23
Characters?24
Strings?25
Bit Strings?25
1.5.2	Syntax Descriptions?28
Exercises?31
2	Scalar Data Types and Operations	33
2.1	Constants and Variables?33
2.1.1	Constant and Variable Declarations?33
2.1.2	Variable Assignment?35
2.2	Scalar Types?36
2.2.1	Type Declarations?36
2.2.2	Integer Types?37
2.2.3	Floating-Point Types?40
2.2.4	Physical Types?41
Time?44
2.2.5	Enumeration Types?45
Characters?46
Booleans?48
Bits?49
Standard Logic?50
Condition Conversion?51
2.3	Type Classification?53
2.3.1	Subtypes?54
2.3.2	Type Qualification?56
2.3.3	Type Conversion?57
2.4	Attributes of Scalar Types?57
2.5	Expressions and Predefined Operations?60
Exercises?64
3	Sequential Statements	67
3.1	If Statements?67
3.1.1	Conditional Variable Assignments?70
3.2	Case Statements?71
3.2.1	Selected Variable Assignments?76
3.3	Null Statements?77
3.4	Loop Statements?78
3.4.1	Exit Statements?79
3.4.2	Next Statements?82
3.4.3	While Loops?83
3.4.4	For Loops?85
3.4.5	Summary of Loop Statements?88
3.5	Assertion and Report Statements?88
Exercises?95
4	Composite Data Types and Operations	97
4.1	Arrays?97
4.1.1	Multidimensional Arrays?100
4.1.2	Array Aggregates?101
4.1.3	Array Attributes?105
4.2	Unconstrained Array Types?107
4.2.1	Predefined Array Types?108
Strings?108
Boolean Vectors, Integer Vectors, and Real Vectors?108
Bit Vectors?109
Standard-Logic Arrays?110
String and Bit-String Literals?110
4.2.2	Unconstrained Array Element Types?111
4.2.3	Unconstrained Array Ports?113
4.3	Array Operations and Referencing?116
4.3.1	Logical Operators?116
4.3.2	Shift Operators?118
4.3.3	Relational Operators?119
Maximum and Minimum Operations?121
4.3.4	The Concatenation Operator?121
4.3.5	To_String Operations?122
4.3.6	Array Slices?122
4.3.7	Array Type Conversions?124
4.3.8	Arrays in Case Statements?126
4.3.9	Matching Case Statements?127
Matching Selected Variable Assignments?129
4.4	Records?130
4.4.1	Record Aggregates?133
4.4.2	Unconstrained Record Element Types?133
Exercises?136
5	Basic Modeling Constructs	139
5.1	Entity Declarations and Architecture Bodies?139
5.1.1	Concurrent Statements?143
5.1.2	Signal Declarations?143
5.2	Behavioral Descriptions?145
5.2.1	Signal Assignment?145
Conditional Signal Assignments?148
Selected Signal Assignments?149
5.2.2	Signal Attributes?151
5.2.3	Wait Statements?153
5.2.4	Delta Delays?157
5.2.5	Transport and Inertial Delay Mechanisms?160
5.2.6	Process Statements?166
5.2.7	Concurrent Signal Assignment Statements?168
Concurrent Simple Signal Assignments?168
Concurrent Conditional Signal Assignment?169
Concurrent Selected Signal Assignments?173
5.2.8	Concurrent Assertion Statements?175
5.2.9	Entities and Passive Processes?176
5.3	Structural Descriptions?178
5.4	Design Processing?189
5.4.1	Analysis?189
5.4.2	Design Libraries and Contexts?191
Context Declarations?193
5.4.3	Elaboration?196
5.4.4	Execution?199
Exercises?200
6	Subprograms	211
6.1	Procedures?211
6.1.1	Return Statement in a Procedure?216
6.2	Procedure Parameters?217
6.2.1	Signal Parameters?221
6.2.2	Default Values?225
6.2.3	Unconstrained Array Parameters?226
6.2.4	Summary of Procedure Parameters?228
6.3	Concurrent Procedure Call Statements?229
6.4	Functions?232
6.4.1	Functional Modeling?234
6.4.2	Pure and Impure Functions?235
6.4.3	The Function now?236
6.5	Overloading?237
6.5.1	Overloading Operator Symbols?238
6.6	Visibility of Declarations?241
Exercises?245
7	Packages and Use Clauses	249
7.1	Package Declarations?249
7.1.1	Subprograms in Package Declarations?254
7.1.2	Constants in Package Declarations?254
7.2	Package Bodies?256
7.2.1	Local Packages?259
7.3	Use Clauses?261
7.3.1	Visibility of Used Declarations?265
Exercises?268
8	Resolved Signals	271
8.1	Basic Resolved Signals?271
8.1.1	Composite Resolved Subtypes?276
8.1.2	Summary of Resolved Subtypes?282
8.1.3	IEEE std_logic_1164 Resolved Subtypes?282
8.2	Resolved Signals and Ports?284
8.2.1	Resolved Ports?286
8.2.2	Driving Value Attribute?289
8.3	Resolved Signal Parameters?290
Exercises?291
9	Predefined and Standard Packages	297
9.1	The Predefined Packages standard and env?297
9.2	IEEE Standard Packages?300
9.2.1	Standard VHDL Mathematical Packages?300
Real Number Mathematical Package?300
Complex Number Mathematical Package?303
9.2.2	The std_logic_1164 Multivalue Logic System?305
9.2.3	Standard Integer Numeric Packages?308
9.2.4	Standard Fixed-Point Packages?318
9.2.5	Standard Floating-Point Packages?323
9.2.6	Package Summary?327
Operator Overloading Summary?327
Conversion Function Summary?330
Strength Reduction Function Summary?337
Exercises?338
10	Case Study: A Pipelined Multiplier Accumulator	361
10.1	Algorithm Outline?361
10.2	A Behavioral Model?364
10.2.1	Testing the Behavioral Model?366
10.3	A Register-Transfer-Level Model?370
10.3.1	Testing the Register-Transfer-Level Model?375
Exercises?378
11	Aliases	381
11.1	Aliases for Data Objects?381
11.2	Aliases for Non-Data Items?386
Exercises?389
12	Generics	391
12.1	Generic Constants?391
12.2	Generic Types?398
12.3	Generic Lists in Packages?402
12.3.1	Local Packages?407
12.3.2	Abstract Data Types using Packages?410
12.4	Generic Lists in Subprograms?415
12.5	Generic Subprograms?420
12.6	Generic Packages?433
Exercises?440
13	Components and Configurations	443
13.1	Components?443
13.1.1	Component Declarations?443
13.1.2	Component Instantiation?445
13.1.3	Packaging Components?446
13.2	Configuring Component Instances?448
13.2.1	Basic Configuration Declarations?448
13.2.2	Configuring Multiple Levels of Hierarchy?451
13.2.3	Direct Instantiation of Configured Entities?454
13.2.4	Generic and Port Maps in Configurations?455
13.2.5	Deferred Component Binding?461
13.3	Configuration Specifications?463
13.3.1	Incremental Binding?465
Exercises?470
14	Generate Statements	475
14.1	Generating Iterative Structures?475
14.2	Conditionally Generating Structures?481
14.2.1	Recursive Structures?488
14.3	Configuration of Generate Statements?491
Exercises?499
15	Access Types	505
15.1	Access Types?505
15.1.1	Access Type Declarations and Allocators?505
15.1.2	Assignment and Equality of Access Values?508
15.1.3	Access Types for Records and Arrays?509
15.2	Linked Data Structures?512
15.2.1	Deallocation and Storage Management?516
15.3	An Ordered-Dictionary ADT Using Access Types?518
Exercises?522
16	Files and Input/Output	525
16.1	Files?525
16.1.1	File Declarations?525
16.1.2	Reading from Files?527
16.1.3	Writing to Files?530
16.1.4	Files Declared in Subprograms?533
16.1.5	Explicit Open and Close Operations?535
16.1.6	File Parameters in Subprograms?538
16.1.7	Portability of Files?540
16.2	The Package Textio?540
16.2.1	Textio Read Operations?544
16.2.2	Textio Write Operations?549
16.2.3	Reading and Writing Other Types?553
Standard Package Read and Write Operations?554
Exercises?556
17	Case Study: A Package for Memories	561
17.1	The Memories Package?561
17.2	Using the Memories Package?572
17.2.1	Common Address and Data Conversions?577
Exercises?584
18	Testbench and Verification Features	585
18.1	External Names?586
18.2	Force and Release Assignments?601
18.3	Embedded PSL in VHDL?609
Exercises?618
19	Shared Variables and Protected Types	621
19.1	Shared Variables and Mutual Exlusion?621
19.2	Uninstantiated Methods in Protected Types?633
Exercises?638
20	Attributes and Groups	641
20.1	Predefined Attributes?641
20.1.1	Attributes of Scalar Types?641
20.1.2	Attributes of Array Types and Objects?642
20.1.3	Attributes Giving Types?643
20.1.4	Attributes of Signals?644
20.1.5	Attributes of Named Items?645
20.2	User-Defined Attributes?654
20.2.1	Attribute Declarations?654
20.2.2	Attribute Specifications?654
20.3	Groups?666
Exercises?668
21	Design for Synthesis	671
21.1	Synthesizable Subsets?671
21.2	Use of Data Types?672
21.2.1	Scalar Types?673
21.2.2	Composite and Other Types?674
21.3	Interpretation of Standard Logic Values?675
21.4	Modeling Combinational Logic?676
21.5	Modeling Sequential Logic?679
21.5.1	Modeling Edge-Triggered Logic?680
21.5.2	Level-Sensitive Logic and Inferring Storage?688
21.5.3	Modeling State Machines?690
21.6	Modeling Memories?692
21.7	Synthesis Attributes?697
21.8	Metacomments?704
Exercises?705
22	Case Study: System Design using the Gumnut Core	709
22.1	Overview of the Gumnut?709
22.1.1	Instruction Set Architecture?709
22.1.2	External Interface?714
The Gumnut Entity Declaration?716
Instruction and Data Memories?717
22.2	A Behavioral Model?721
22.2.1	The Gumnut Definitions Package?721
22.2.2	The Gumnut Behavioral Architecture Body?727
Overview of the Interpreter?730
Resetting the Interpreter?731
Acknowledging an Interrupt?732
Fetching an Instruction?732
Performing an Arithmetic/Logical Operation?733
Performing a Shift Operation?734
Performing a Memory-I/O Instruction?735
Performing a Branch Instruction?737
Performing a Jump Instruction?738
Performing a Miscellaneous Instruction?738
22.2.3	Verifying the Behavioral Model?739
22.3	A Register-Transfer-Level Model?745
22.3.1	The Architecture Body?747
22.3.2	Verifying the RTL Model?762
22.4	A Digital Alarm Clock?762
22.4.1	System Design?763
22.4.2	Synthesizing and Implementing the Alarm Clock?770
Exercises?772
23	Miscellaneous Topics	775
23.1	Guards and Blocks?775
23.1.1	Guarded Signals and Disconnection?775
The Driving Attribute?779
Guarded Ports?780
Guarded Signal Parameters?781
23.1.2	Blocks and Guarded Signal Assignment?781
Explicit Guard Signals?784
Disconnection Specifications?785
23.1.3	Using Blocks for Structural Modularity?786
External Names and Blocks?789
Generics and Ports in Blocks?790
Configuring Designs with Blocks?790
23.2	IP Encryption?792
23.2.1	Key Exchange?811
23.3	VHDL Procedural Interface (VHPI)?812
23.3.1	Direct Binding?813
23.3.2	Tabular Registration and Indirect Binding?815
23.3.3	Registration of Applications and Libraries?817
23.4	Postponed Processes?818
23.5	Conversion Functions in Association Lists?821
23.6	Linkage Ports?827
Exercises?828
A	Standard Packages	835
A.1	The Predefined Package standard?835
A.2	The Predefined Package env?839
A.3	The Predefined Package textio?839
A.4	Standard VHDL Mathematical Packages?841
A.4.1	The math_real Package?841
A.4.2	The math_complex Package?843
A.5	The std_logic_1164 Multivalue Logic System Package?844
A.6	Standard Integer Numeric Packages?848
A.6.1	The numeric_bit Package?848
A.6.2	The numeric_std Package?855
A.6.3	The numeric_bit_unsigned Package?856
A.6.4	The numeric_std_unsigned Package?858
A.7	Standard Fixed-Point Packages?859
A.7.1	The fixed_float_types Package?860
A.7.2	The fixed_generic_pkg Package?860
A.7.3	The fixed_pkg Package?872
A.8	Standard Floating-Point Packages?872
A.8.1	The float_generic_pkg Package?873
A.8.2	The float_pkg Package?884
B	VHDL Syntax	885
B.1	Design File?887
B.2	Library Unit Declarations?887
B.3	Declarations and Specifications?889
B.4	Type Definitions?892
B.5	Concurrent Statements?894
B.6	Sequential Statements?896
B.7	Interfaces and Associations?899
B.8	Expressions and Names?900
C	Answers to Exercises	903
References	933
Index	935

Library of Congress Subject Headings for this publication:

VHDL (Computer hardware description language).
Electronic digital computers -- Computer simulation.