Table of contents for Microelectronic circuit design / Richard C. Jaeger, Travis N. Blalock.

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CONTENTS
Preface xix
P A R T O N E
SOLID STATE ELECTRONIC
AND DEVICES
C H A P T E R 1
INTRODUCTION TO ELECTRONICS 1
1.1 A Brief History of Electronics: From
Vacuum Tubes to Ultra-Large-Scale
Integration 3
1.2 Classification of Electronic Signals 8
1.2.1 Digital Signals 8
1.2.2 Analog Signals 9
1.2.3 A/D and D/A Converters?Bridging
the Analog and Digital Domains 10
1.3 Notational Conventions 12
1.4 Problem-Solving Approach 13
What Are Reasonable Numbers? 15
1.5 Important Concepts from Circuit
Theory 15
1.5.1 Voltage and Current Division 15
1.5.2 Th?evenin and Norton Circuit
Representations 17
1.6 Frequency Spectrum of Electronic
Signals 22
1.7 Amplifiers 24
1.7.1 Ideal Operational Amplifiers 25
1.7.2 Amplifier Frequency
Response 28
1.8 Element Variations in Circuit Design 29
1.8.1 Mathematical Modeling
of Tolerances 29
1.8.2 Worst-Case Analysis 30
1.8.3 Monte Carlo Analysis 32
1.8.4 Temperature Coefficients 36
1.9 Numeric Precision 37
Summary 37
Key Terms 39
References 40
Additional Reading 40
Problems 40
C H A P T E R 2
SOLID-STATE ELECTRONICS 45
2.1 Solid-State Electronic Materials 47
2.2 Covalent Bond Model 49
2.3 Drift Currents and Mobility in
Semiconductors 52
2.3.1 Drift Currents 52
2.3.2 Mobility 53
2.3.3 Velocity Saturation
(Advanced Topic) 53
2.4 Resistivity of Intrinsic Silicon 54
2.5 Impurities in Semiconductors 56
2.5.1 Donor Impurities in Silicon 56
2.5.2 Acceptor Impurities in Silicon 56
2.6 Electron and Hole Concentrations in Doped
Semiconductors 57
2.6.1 n-Type Material (ND > NA ) 58
2.6.2 p-Type Material (NA > ND ) 58
2.7 Mobility and Resistivity in Doped
Semiconductors 60
2.8 Diffusion Currents 64
2.9 Total Current 65
2.10 Energy Band Model 66
2.10.1 Electron?Hole Pair Generation in an
Intrinsic Semiconductor 66
2.10.2 Energy Band Model for a Doped
Semiconductor 67
2.10.3 Compensated Semiconductors 67
2.11 Overview of Integrated Circuit Fabrication 69
Summary 72
Key Terms 74
References 75
Additional Reading 75
Problems 76
C H A P T E R 3
SOLID-STATE DIODES AND
DIODE CIRCUITS 80
3.1 The pn Junction Diode 81
3.1.1 pn Junction Electrostatics 82
3.1.2 Internal Diode Currents 86
vii
viii Contents
3.2 The i-v Characteristics of the Diode 87
3.3 The Diode Equation: A Mathematical Model
for the Diode 90
3.4 Diode Characteristics Under Reverse, Zero, and
Forward Bias 93
3.4.1 Reverse Bias 93
3.4.2 Zero Bias 94
3.4.3 Forward Bias 94
3.5 Diode Temperature Coefficient 96
3.6 Diodes Under Reverse Bias 98
3.6.1 Saturation Current in Real Diodes 99
3.6.2 Reverse Breakdown 100
3.6.3 Diode Model for the Breakdown
Region 101
3.7 pn Junction Capacitance 101
3.7.1 Reverse Bias 102
3.7.2 Forward Bias 102
3.8 Schottky Barrier Diode 103
3.9 Diode SPICE Model and Layout 104
3.10 Diode Circuit Analysis 106
3.10.1 Load-Line Analysis 106
3.10.2 Analysis Using the Mathematical Model
for the Diode 108
3.10.3 The Ideal Diode Model 113
3.10.4 Constant Voltage Drop Model 115
3.10.5 Model Comparison and
Discussion 116
3.11 Multiple-Diode Circuits 117
3.11.1 A Two-Diode Circuit 117
3.11.2 A Three-Diode Circuit 120
3.12 Analysis of Diodes Operating in the Breakdown
Region 123
3.12.1 Load-Line Analysis 123
3.12.2 Analysis with the Piecewise Linear
Model 124
3.12.3 Voltage Regulation 124
3.12.4 Analysis Including Zener
Resistance 125
3.12.5 Line and Load Regulation 126
3.13 Half-Wave Rectifier Circuits 127
3.13.1 Half-Wave Rectifier with Resistor
Load 128
3.13.2 Rectifier Filter Capacitor 129
3.13.3 Half-Wave Rectifier with RC Load 130
3.13.4 Ripple Voltage and Conduction
Interval 131
3.13.5 Diode Current 134
3.13.6 Surge Current 135
3.13.7 Peak-Inverse-Voltage (PIV) Rating 136
3.13.8 Diode Power Dissipation 136
3.13.9 Half-Wave Rectifier with Negative
Output Voltage 137
3.14 Full-Wave Rectifier Circuits 137
3.14.1 Full-Wave Rectifier with Negative
Output Voltage 139
3.15 Full-Wave Bridge Rectification 139
3.16 Rectifier Comparison and Design Tradeoffs 140
3.17 Three-Terminal IC Voltage Regulators 142
3.18 dc-to-dc Converters (Advanced Topic) 146
3.18.1 The Boost Converter 146
3.18.2 The Buck Converter 149
3.19 Wave-Shaping Circuits 152
3.19.1 The Clamping or dc-Restoring
Circuit 152
3.19.2 Clipping or Limiting Circuits 153
3.19.3 Dual Clipping Levels 154
3.19.4 Piecewise Linear Voltage Transfer
Characteristics 155
3.20 Dynamic Switching Behavior of
the Diode 155
3.21 Photo Diodes, Solar Cells, and Light-Emitting
Diodes 157
3.21.1 Photo Diodes and Photodetectors 157
3.21.2 Power Generation from Solar
Cells 158
3.21.3 Light-Emitting Diodes (LEDs) 159
Summary 160
Key Terms 162
References 162
Additional Reading 163
Problems 163
C H A P T E R 4
FIELD-EFFECT TRANSISTORS 176
4.1 Characteristics of the MOS Capacitor 178
4.1.1 Accumulation Region 178
4.1.2 Depletion Region 178
4.1.3 Inversion Region 179
4.2 The NMOS Transistor 180
4.2.1 Qualitative i-v Behavior of the NMOS
Transistor 181
4.2.2 Triode Region Characteristics of the
NMOS Transistor 183
4.2.3 On Resistance 186
4.2.4 Use of the MOSFET as a
Voltage-Controlled Resistor 187
4.2.5 Saturation of the i-v
Characteristics 188
4.2.6 Mathematical Model in the Saturation
(Pinch-Off) Region 189
4.2.7 Transconductance 192
4.2.8 Channel-Length Modulation 192
Contents ix
4.2.9 Transfer Characteristics
and Depletion-Mode
MOSFETS 194
4.2.10 Body Effect or Substrate
Sensitivity 195
4.3 PMOS Transistors 197
4.4 MOSFET Circuit Symbols 199
4.5 MOS Transistor Fabrication and Layout
Design Rules 202
4.5.1 Minimum Feature Size and Alignment
Tolerance 202
4.5.2 MOS Transistor Layout 202
4.6 Capacitances in MOS Transistors 205
4.6.1 NMOS Transistor Capacitances in the
Triode Region 205
4.6.2 Capacitances in the Saturation
Region 206
4.6.3 Capacitances in Cutoff 207
4.7 MOSFET Modeling in SPICE 207
4.8 Biasing the NMOS Field-Effect Transistor 209
4.9 Biasing the PMOS Field-Effect Transistor 228
4.10 Current Sources and the MOS Current
Mirror 232
4.10.1 dc Analysis of the NMOS Current
Mirror 234
4.10.2 Changing the MOS Mirror Ratio 236
4.10.3 Output Resistance of the Current
Mirror 237
4.10.4 Current Mirror Layout 238
4.10.5 Multiple Current Mirrors 239
4.11 MOS Transistor Scaling 243
4.11.1 Drain Current 243
4.11.2 Gate Capacitance 243
4.11.3 Circuit and Power Densities 244
4.11.4 Power-Delay Product 244
4.11.5 Cutoff Frequency 245
4.11.6 High Field Limitations 246
4.11.7 Subthreshold Conduction 246
4.12 The Junction Field-Effect Transistor (JFET)
(Advanced Topic) 247
4.12.1 The JFET with Bias Applied 248
4.12.2 JFET Channel with Drain-Source
Bias 248
4.12.3 n-Channel JFET i -v Characteristics 251
4.12.4 The p-Channel JFET 252
4.12.5 Circuit Symbols and JFET Model
Summary 252
4.12.6 JFET Capacitances 254
4.13 JFET MODELING IN SPICE 254
4.14 Biasing the JFET and Depletion-Mode
MOSFET 255
Summary 258
Key Terms 260
References 261
Problems 261
C H A P T E R 5
BIPOLAR JUNCTION TRANSISTORS 274
5.1 Physical Structure of the Bipolar Transistor 276
5.2 The Transport Model for the npn Transistor 277
5.2.1 Forward Characteristics 277
5.2.2 Reverse Characteristics 279
5.2.3 The Complete Transport Model
Equations for Arbitrary Bias
Conditions 281
5.3 The pnp Transistor 283
5.4 Equivalent Circuit Representations for the
Transport Models 285
5.5 The Ebers-Moll Model (*Advanced Topic) 286
5.5.1 Forward Characteristics of the npn
Transistor 287
5.5.2 Reverse Characteristics of the npn
Transistor 287
5.5.3 The Ebers-Moll Model for the npn
Transistor 287
5.5.4 The Ebers-Moll Model for the pnp
Transistor 288
5.5.5 Equivalent Circuit Representations for
the Ebers-Moll Models 288
5.6 The Operating Regions of the Bipolar
Transistor 289
5.7 The i-v Characteristics of the Bipolar
Transistor 290
5.7.1 Output Characteristics 291
5.7.2 Transfer Characteristics 293
5.7.3 Junction Breakdown Voltages 294
5.8 Minority-Carrier Transport in the Base
Region 295
5.8.1 Base Transit Time 296
5.8.2 Diffusion Capacitance 298
5.9 Transport Model Simplifications 299
5.9.1 Simplified Model for the Cutoff
Region 299
5.9.2 Model Simplifications for the
Forward-Active Region 302
5.9.3 Frequency Dependence of the
Common-Emitter Current Gain 306
5.9.4 Transconductance 307
5.9.5 Simplified Model for the Reverse-Active
Region 311
5.9.6 Modeling Operation in the Saturation
Region 313
5.10 The Early Effect and Early Voltage 316
5.10.1 Modeling the Early Effect 317
5.10.2 Origin of the Early Effect 317
5.11 Bipolar Technology and SPICE Model 318
5.11.1 Qualitative Description 318
5.11.2 SPICE Model Equations 318
5.11.3 High-Performance Bipolar
Transistors 321
x Contents
5.12 Practical Bias Circuits for the BJT 322
5.12.1 Four-Resistor Bias Network 322
5.12.2 Design Objectives for the Four-Resistor
Bias Network 325
5.13 Current Sources and the Bipolar Current
Mirror 330
5.13.1 Bipolar Transistor Current Mirror 331
5.13.2 Current Mirror Analysis 331
5.13.3 Altering the BJT Current Mirror
Ratio 333
5.13.4 Output Resistance of the Current
Mirror 335
5.14 Tolerances in Bias Circuits 336
5.14.1 Worst-Case Analysis 337
5.14.2 Monte Carlo Analysis 339
Summary 343
Key Terms 344
References 345
Problems 345
P A R T T W O
DIGITAL ELECTRONICS 357
C H A P T E R 6
INTRODUCTION TO DIGITAL
ELECTRONICS 359
6.1 Ideal Logic Gates 361
6.2 Logic Level Definitions and
Noise Margins 362
6.2.1 Logic Voltage Levels 363
6.2.2 Noise Margins 364
6.2.3 Logic Gate Design Goals 365
6.3 Dynamic Response of Logic Gates 365
6.3.1 Rise Time and Fall Times 366
6.3.2 Propagation Delay 367
6.3.3 Power-Delay Product 367
6.4 Review of Boolean Algebra 368
6.5 Diode Logic and DTL 371
6.5.1 Diode OR Gate 371
6.5.2 Diode AND Gate 372
6.5.3 A Diode-Transistor Logic (DTL)
Gate 372
6.6 NMOS Logic Design 373
6.6.1 NMOS Inverter with Resistive
Load 374
6.6.2 Design of the W/L Ratio of MS 375
6.6.3 Load Resistor Design 376
6.6.4 Load-Line Visualization 376
6.6.5 On-Resistance of the Switching
Device 378
6.6.6 Noise Margin Analysis 380
6.6.7 Calculation of VI L and VO H 380
6.6.8 Calculation of VI H and VO L 381
6.6.9 Load Resistor Problems 383
6.6.10 Transistor Alternatives to the Load
Resistor 383
6.7 Static Design of the NMOS Saturated Load
Inverter 384
6.7.1 Calculation of VH 386
6.7.2 Calculation of (W/L)S 387
6.7.3 Noise Margin Analysis 394
6.8 NMOS Inverter with a Linear Load Device 397
6.9 NMOS Inverter with a Depletion-Mode Load 398
6.9.1 Design of the W/L Ratio of ML 399
6.9.2 Design of the W/L Ratio of MS 399
6.9.3 Noise Margins for the Inverter with
Depletion-Mode Load 400
6.10 NMOS Inverter Summary and Comparison 406
6.11 NMOS NAND and NOR Gates 407
6.11.1 NOR Gates 407
6.11.2 NAND Gates 408
6.11.3 NOR and NAND Gate Layouts in NMOS
Depletion-Mode Technology 410
6.12 Complex NMOS Logic Design 412
6.12.1 Selecting Between the Two
Designs 414
6.13 Power Dissipation 416
6.13.1 Static Power Dissipation 416
6.13.2 Dynamic Power Dissipation 417
6.13.3 Power Scaling in MOS Logic Gates 419
6.14 Dynamic Behavior of MOS Logic Gates 420
6.14.1 Capacitances in Logic Circuits 420
6.14.2 Dynamic Response of the NMOS
Inverter with a Resistive Load 421
6.14.3 NMOS Inverter with a Depletion-Mode
Load 429
6.14.4 NMOS Inverter with a Saturated
Load 434
6.15 A Final Comparison of Load Devices 437
6.16 PMOS Logic 442
6.16.1 PMOS Inverters 443
6.16.2 NOR and NAND Gates 443
Summary 445
Key Terms 448
References 448
Additional Reading 449
Problems 449
C H A P T E R 7
COMPLEMENTARY MOS (CMOS)
LOGIC DESIGN 462
7.1 CMOS Inverter Technology 463
7.1.1 CMOS Inverter Layout 465
Contents xi
7.2 Static Characteristics of the CMOS Inverter 466
7.2.1 CMOS Voltage Transfer
Characteristics 467
7.2.2 Noise Margins for the CMOS
Inverter 469
7.3 Dynamic Behavior of the CMOS Inverter 472
7.3.1 Propagation Delay Estimate 472
7.3.2 Rise and Fall Times 474
7.3.3 Delay of Cascaded Inverters 476
7.4 Power Dissipation and Power Delay Product
in CMOS 478
7.4.1 Static Power Dissipation 478
7.4.2 Dynamic Power Dissipation 478
7.4.3 Power-Delay Product 479
7.5 CMOS NOR and NAND Gates 480
7.5.1 CMOS NOR Gate 481
7.5.2 CMOS NAND Gates 484
7.6 Design of Complex Gates in CMOS 485
7.7 Minimum Size Gate Design and
Performance 491
7.8 Dynamic Domino CMOS Logic 493
7.9 Cascade Buffers 496
7.9.1 Cascade Buffer Delay Model 496
7.9.2 Optimum Number of Stages 497
7.10 The CMOS Transmission Gate 500
7.11 CMOS Latchup 501
Summary 504
Key Terms 505
References 506
Problems 506
C H A P T E R 8
MOS MEMORY AND STORAGE CIRCUITS 515
8.1 Random Access Memory 516
8.1.1 Random Access Memory (RAM)
Architecture 517
8.1.2 A 256-Mb Memory Chip 517
8.2 Static Memory Cells 519
8.2.1 Memory Cell Isolation and Access?
The 6-T Cell 520
8.2.2 The Read Operation 521
8.2.3 Writing Data into the 6-T Cell 525
8.3 Dynamic Memory Cells 528
8.3.1 The One-Transistor Cell 528
8.3.2 Data Storage in the 1-T Cell 528
8.3.3 Reading Data from the 1-T Cell 530
8.3.4 The Four-Transistor Cell 532
8.4 Sense Amplifiers 533
8.4.1 A Sense Amplifier for the 6-T Cell 533
8.4.2 A Sense Amplifier for the 1-T Cell 536
8.4.3 The Boosted Wordline Circuit 538
8.4.4 Clocked CMOS Sense Amplifiers 539
8.5 Address Decoders 540
8.5.1 NOR Decoder 541
8.5.2 NAND Decoder 542
8.5.3 Decoders in Domino CMOS Logic 543
8.5.4 Pass-Transistor Column Decoder 544
8.6 Read-Only Memory (ROM) 546
8.7 Flip-Flops 551
8.7.1 RS Flip-Flop 551
8.7.2 The D-Latch Using Transmission
Gates 553
8.7.3 A Master-Slave D Flip-Flop 554
Summary 555
Key Terms 555
References 556
Problems 557
C H A P T E R 9
BIPOLAR LOGIC CIRCUITS 563
9.1 The Current Switch (Emitter-Coupled Pair) 564
9.1.1 Mathematical Model for Static Behavior
of the Current Switch 565
9.1.2 Current Switch Analysis
for vI >VREF 566
9.1.3 Current Switch Analysis
for vI <VREF 567
9.2 The Emitter-Coupled Logic (ECL) Gate 568
9.2.1 ECL Gate with vI =VH 569
9.2.2 ECL Gate with vI =VL 570
9.2.3 Input Current of the ECL Gate 570
9.2.4 ECL Summary 570
9.3 Noise Margin Analysis for the ECL Gate 571
9.3.1 VI L , VO H , VI H , and VO L 571
9.3.2 Noise Margins 573
9.4 Current Source Implementation 574
9.5 The ECL OR-NOR Gate 578
9.6 The Emitter Follower 580
9.6.1 Emitter Follower with Resistor
Bias 581
9.6.2 Emitter Follower with a Load
Resistor 582
9.7 ?Emitter Dotting?? or ?Wired-OR?? Logic 585
9.7.1 Parallel Connection of Emitter-Follower
Outputs 585
9.7.2 The Wired-OR Logic Function 586
9.8 Design of Reference Voltage Circuits 586
9.8.1 Temperature Compensation 588
9.9 Diodes in Bipolar Integrated Circuits 589
9.10 ECL Power-Delay Characteristics 590
9.10.1 Power Dissipation 590
9.10.2 Gate Delay 592
9.10.3 Power-Delay Product 594
xii Contents
9.11 The Saturating Bipolar Inverter 597
9.11.1 Static Inverter Characteristics 598
9.11.2 Saturation Voltage of the Bipolar
Transistor 598
9.11.3 Load-Line Visualization 601
9.11.4 Switching Characteristics of the
Saturated BJT 602
9.12 A Transistor-Transistor Logic (TTL)
Prototype 605
9.12.1 TTL Inverter for vI =VL 605
9.12.2 TTL Inverter for vI =VH 606
9.12.3 Power in the Prototype TTL Gate 607
9.12.4 VIH, VIL, and Noise Margins for the TTL
Prototype 608
9.12.5 Prototype Inverter Summary 610
9.12.6 Fanout Limitations of the TTL
Prototype 610
9.13 The Standard 7400 Series TTL Inverter 614
9.13.1 Analysis for vI =VL 614
9.13.2 Analysis for vI =VH 615
9.13.3 Power Consumption 617
9.13.4 TTL Propagation Delay and
Power-Delay Product 617
9.13.5 TTL Voltage Transfer Characteristic and
Noise Margins 618
9.13.6 Fanout Limitations of Standard
TTL 619
9.14 Logic Functions in TTL 619
9.14.1 Multi-Emitter Input Transistors 620
9.14.2 TTL NAND Gates 621
9.14.3 Input Clamping Diodes 622
9.15 Schottky-Clamped TTL 623
9.16 Comparison of the Power-Delay Products of ECL
and TTL 626
9.17 BiCMOS Logic 626
9.17.1 BiCMOS Buffers 627
9.17.2 BiNMOS Inverters 629
9.17.3 BiCMOS Logic Gates 631
Summary 632
Key Terms 634
References 634
Additional Reading 634
Problems 634
P A R T T H R E E
ANALOG CIRCUIT DESIGN 647
C H A P T E R 10
ANALOG SYSTEMS 649
10.1 An Example of an Analog Electronic System 650
10.2 Amplification 651
10.2.1 Voltage Gain 653
10.2.2 Current Gain 653
10.2.3 Power Gain 654
10.2.4 The Decibel Scale 654
10.3 Amplifier Biasing for Linear Operation 655
10.4 Distortion in Amplifiers 658
10.5 Two-Port Models for Amplifiers 661
10.5.1 The g-parameters 661
10.5.2 The Hybrid or h-parameters 665
10.5.3 The Admittance or y-parameters 670
10.5.4 The Impedance or z-parameters 673
10.6 Mismatched Source and Load Resistances 677
10.6.1 Voltage Amplifiers 677
10.6.2 Current Amplifiers 678
10.7 Amplifier Transfer Functions and Frequency
Response 679
10.7.1 Bode Plots 680
10.7.2 The Low-Pass Amplifier 681
10.7.3 The High-Pass Amplifier 686
10.7.4 Band-Pass Amplifiers 689
10.7.5 Narrow-Band or High-Q Band-Pass
Amplifiers 692
10.7.6 Band-Rejection Amplifiers 693
10.7.7 The All-Pass Function 694
10.7.8 More Complex Transfer Functions 695
Summary 697
Key Terms 698
References 699
Problems 699
C H A P T E R 11
OPERATIONAL AMPLIFIERS 705
11.1 The Differential Amplifier 706
11.1.1 Differential Amplifier Model 707
11.1.2 The Ideal Differential Amplifier 709
11.2 The Ideal Operational Amplifier 710
11.2.1 Assumptions for Ideal Operational
Amplifier Analysis 710
11.3 Analysis of Circuits Containing Ideal Operational
Amplifiers 711
11.3.1 The Inverting Amplifier 711
11.3.2 The Noninverting Amplifier 715
11.3.3 The Unity-Gain Buffer, or Voltage
Follower 718
11.3.4 The Summing Amplifier 720
11.3.5 The Difference Amplifier 721
11.3.6 The Instrumentation Amplifier 724
11.3.7 An Active Low-Pass Filter 726
11.3.8 The Integrator 729
11.3.9 Differentiation 730
11.3.10 Cascaded Amplifiers 731
11.3.11 Amplifier Terminology Review 733
Contents xiii
11.4 Nonideal Operational Amplifiers 734
11.4.1 Finite Open-Loop Gain 734
11.4.2 Gain Error 736
11.4.3 Nonzero Output Resistance 737
11.4.4 Finite Input Resistance 742
11.4.5 Summary of Nonideal Inverting and
Noninverting Amplifiers 746
11.4.6 Finite Common-Mode Rejection
Ratio 746
11.4.7 Common-Mode Input Resistance 752
11.4.8 DC Error Sources 753
11.4.9 Output Voltage and Current Limits 759
11.5 Frequency Response and Bandwidth
of Operational Amplifiers 764
11.5.1 Frequency Response of the
Noninverting Amplifier 766
11.5.2 Inverting Amplifier Frequency
Response 768
11.5.3 Frequency Response of Cascaded
Amplifiers 771
11.5.4 Large-Signal Limitations?Slew Rate
and Full-Power Bandwidth 779
11.5.5 Macro Model for Operational Amplifier
Frequency Response 780
11.5.6 Complete Op Amp Macro Models
in SPICE 781
11.5.7 Examples of Commercial
General-Purpose Operational
Amplifiers 781
Summary 784
Key Terms 785
References 786
Additional Reading 786
Problems 786
C H A P T E R 12
OPERATIONAL AMPLIFIER
APPLICATIONS 800
12.1 Active Filters 801
12.1.1 Low-Pass Filter 801
12.1.2 Sensitivity 805
12.1.3 A High-Pass Filter with Gain 806
12.1.4 Band-Pass Filter 808
12.1.5 The Tow-Thomas Biquad 811
12.1.6 Magnitude and Frequency Scaling 815
12.2 Switched-Capacitor Circuits 817
12.2.1 A Switched-Capacitor Integrator 817
12.2.2 Noninverting SC Integrator 819
12.2.3 Switched-Capacitor Filters 821
12.3 Digital-to-Analog Conversion 824
12.3.1 D/A Converter Fundamentals 824
12.3.2 D/A Converter Errors 825
12.3.3 Digital-to-Analog Converter
Circuits 828
12.4 Analog-to-Digital Conversion 835
12.4.1 A/D Converter Fundamentals 836
12.4.2 Analog-to-Digital Converter Errors 837
12.4.3 Basic A/D Conversion Techniques 838
12.5 Nonlinear Circuit Applications 851
12.5.1 A Precision Half-Wave Rectifier 851
12.5.2 Nonsaturating Precision-Rectifier
Circuit 852
12.5.3 An AC Voltmeter 853
12.6 Circuits Using Positive Feedback 854
12.6.1 The Comparator and Schmitt
Trigger 854
12.6.2 The Astable Multivibrator 857
12.6.3 The Monostable Multivibrator or One
Shot 859
Summary 861
Key Terms 863
References 863
Additional Reading 864
Problems 864
C H A P T E R 13
SMALL-SIGNAL MODELING AND
LINEAR AMPLIFICATION 871
13.1 The Transistor as an Amplifier 873
13.1.1 The BJT Amplifier 873
13.1.2 The MOSFET Amplifier 875
13.2 Coupling and Bypass Capacitors 876
13.3 Circuit Analysis Using dc and ac Equivalent
Circuits 878
13.3.1 Menu for dc and ac Analysis 879
13.4 Introduction to Small-Signal Modeling 883
13.4.1 Graphical Interpretation of the
Small-Signal Behavior of the
Diode 883
13.4.2 Small-Signal Modeling
of the Diode 885
13.4.3 A Current-Controlled Attenuator 887
13.5 Small-Signal Models for Bipolar Junction
Transistors 888
13.5.1 The Hybrid-Pi Model 891
13.5.2 Small-Signal Current Gain 891
13.5.3 The Amplification Factor
of the BJT 892
13.5.4 Equivalent Forms of the Small-Signal
Model 894
13.5.5 Definition of a Small Signal for
the Bipolar Transistor 894
13.5.6 Small-Signal Model for the
pnp Transistor 896
13.5.7 ac Analysis Versus Transient Analysis
in SPICE 897
xiv Contents
13.6 The BJT Common-Emitter (C-E)
Amplifier 897
13.6.1 Voltage Gain of the Common-Emitter
Amplifier 899
13.6.2 Model Simplifications 902
13.6.3 A Design Guide for the Common-Emitter
Amplifier with Resistive Load 903
13.6.4 Common-Emitter Voltage Gain Upper
Bound 904
13.7 Small-Signal Models for Field-Effect
Transistors 907
13.7.1 Small-Signal Model for
the MOSFET 907
13.7.2 Amplification Factor of
the MOSFET 910
13.7.3 Definition of Small-Signal Operation
for the MOSFET 911
13.7.4 Body Effect in the Four-Terminal
MOSFET 912
13.7.5 Small-Signal Model for the PMOS
Transistor 913
13.7.6 Small-Signal Model for the Junction
Field-Effect Transistor 914
13.8 Summary and Comparison of the Small-Signal
Models of the BJT and FET 916
13.9 The Common-Source Amplifier 917
13.9.1 Voltage Gain of the Common-Source
Amplifier 917
13.9.2 A Design Guide for the Common-Source
Amplifier with Resistive Load 923
13.10 Input and Output Resistances of the
Common-Emitter and Common-Source
Amplifiers 925
13.10.1 Common-Emitter Input
Resistance 926
13.10.2 Common-Source Input Resistance 928
13.10.3 Common-Emitter Output
Resistance 929
13.10.4 Common-Source Output
Resistance 930
13.11 Examples of Common-Emitter and
Common-Source Amplifiers 931
13.11.1 A Common-Emitter Amplifier 931
13.11.2 ac Versus Transient Analysis in SPICE?
Another Visit 936
13.11.3 A MOSFET Common-Source
Amplifier 937
13.11.4 A JFET Common-Source Amplifier 943
13.11.5 Comparison of the Three Amplifier
Examples 947
13.11.6 Common-Emitter and Common-Source
Amplifier Summary 948
13.11.7 Guidelines for Neglecting the Transistor
Output Resistance 949
13.12 Amplifier Power and Signal Range 949
13.12.1 Power Dissipation 949
13.12.2 Signal Range 951
Summary 954
Key Terms 955
Problems 956
C H A P T E R 14
SINGLE-TRANSISTOR AMPLIFIERS 968
14.1 Amplifier Classification 969
14.1.1 Signal Injection and Extraction?
The BJT 970
14.1.2 Signal Injection and Extraction?
The FET 971
14.1.3 Generalized Common-Emitter (C-E) and
Common-Source (C-S) Amplifiers 971
14.1.4 Common-Collector (C-C) and
Common-Drain (C-D) Topologies 973
14.1.5 Common-Base (C-B) and Common-Gate
(C-G) Amplifiers 974
14.2 Inverting Amplifiers?Common-Emitter and
Common-Source Circuits 975
14.2.1 Terminal Voltage Gain 976
14.2.2 Input Resistance 977
14.2.3 Signal Source Voltage Gain 977
14.2.4 Important Limits 978
14.2.5 Output Resistance 982
14.2.6 Increased Signal Range 986
14.2.7 Satisfying the Condition gmRE _ 1
or gmRS _ 1 987
14.2.8 Current Gain 988
14.2.9 C-E/C-S Amplifier Summary 988
14.2.10 Equivalent Transistor Representation
of the Generalized C-E/C-S
Transistor 989
14.3 Follower Circuits?Common-Collector and
Common-Drain Amplifiers 990
14.3.1 Terminal Voltage Gain 990
14.3.2 Input Resistance 992
14.3.3 Signal Source Voltage Gain 992
14.3.4 Follower Signal Range 994
14.3.5 Output Resistance 995
14.3.6 Current Gain 997
14.3.7 C-C/C-D Amplifier Summary 998
14.4 Noninverting Amplifiers?Common-Base
and Common-Gate Circuits 999
14.4.1 Terminal Voltage Gain and Input
Resistance 999
14.4.2 Signal Source Voltage Gain 1000
14.4.3 Input Signal Range 1004
14.4.4 Output Resistance 1004
14.4.5 Current Gain 1005
14.4.6 C-B/C-G Amplifier Summary 1006
Contents xv
14.5 Amplifier Prototype Review and
Comparison 1007
14.5.1 The BJT Amplifiers 1007
14.5.2 The FET Amplifiers 1010
14.6 Coupling and Bypass Capacitor Design 1016
14.6.1 Common-Emitter and Common-Source
Amplifiers 1016
14.6.2 Common-Collector and Common-Drain
Amplifiers 1021
14.6.3 Common-Base and Common-Gate
Amplifiers 1023
14.6.4 Setting Lower Cutoff Frequency
fL 1027
14.7 Amplifier Design Examples 1028
14.7.1 Monte Carlo Evaluation of the
Common-Base Amplifier Design 1038
14.8 The Influence of Body Effect on Amplifier
Performance 1044
14.8.1 Common-Source Amplifier 1044
14.8.2 Common-Drain Amplifier 1046
14.8.3 Common-Gate Amplifier 1047
Summary 1050
Key Terms 1051
Additional Reading 1052
Problems 1052
C H A P T E R 15
MULTISTAGE AMPLIFIERS 1065
15.1 Multistage ac-Coupled Amplifiers 1066
15.1.1 Voltage Gain 1068
15.1.2 Input Resistance 1070
15.1.3 Signal Source Voltage Gain 1070
15.1.4 Output Resistance 1071
15.1.5 Current and Power Gain 1072
15.1.6 Input Signal Range 1073
15.1.7 Improving Amplifier Voltage
Gain 1077
15.1.8 The Common-Emitter Cascade 1077
15.2 Direct-Coupled Amplifiers 1079
15.2.1 Analysis of a dc-Coupled
Amplifier 1079
15.2.2 dc Analysis 1080
15.2.3 ac Analysis 1083
15.2.4 Compound Transistor
Configurations?The Darlington and
Cascode Circuits 1084
15.3 Differential Amplifiers 1087
15.3.1 Bipolar and MOS Differential
Amplifiers 1088
15.3.2 dc Analysis of the Bipolar Differential
Amplifier 1088
15.3.3 Small-Signal Transfer Characteristic for
the Bipolar Differential Amplifier 1091
15.3.4 ac Analysis of the Bipolar Differential
Amplifier 1091
15.3.5 Differential-Mode Gain and Input
Resistance 1093
15.3.6 Common-Mode Gain and Input
Resistance 1095
15.3.7 Common-Mode Rejection Ratio
(CMRR) 1097
15.3.8 Analysis Using Differential- and
Common-Mode Half-Circuits 1098
15.3.9 Biasing with Electronic Current
Sources 1102
15.3.10 Modeling the Electronic Current Source
in SPICE 1103
15.3.11 dc Analysis of the MOSFET Differential
Amplifier 1103
15.3.12 Differential-Mode Input Signals 1105
15.3.13 Small-Signal Transfer Characteristic
for the MOS Differential
Amplifier 1106
15.3.14 Common-Mode Input Signals 1107
15.3.15 Two-Port Model for Differential
Pairs 1108
15.4 Evolution to Basic Operational Amplifiers 1110
15.4.1 A Two-Stage Prototype for an
Operational Amplifier 1113
15.4.2 Improving the Op Amp Voltage
Gain 1119
15.4.3 Output Resistance Reduction 1120
15.4.4 A CMOS Operational Amplifier
Prototype 1126
15.4.5 BiCMOS Amplifiers 1127
15.5 Output Stages 1128
15.5.1 The Source Follower?Class-A Output
Stage 1128
15.5.2 Source Follower with External Load
Resistor 1129
15.5.3 Class-B Push-Pull Output Stage 1131
15.5.4 Class-AB Amplifiers 1132
15.5.5 Class-AB Output Stages for Operational
Amplifiers 1134
15.5.6 Short-Circuit Protection 1134
15.5.7 Transformer Coupling 1136
15.6 Electronic Current Sources 1140
15.6.1 Single-Transistor Current
Sources 1141
15.6.2 Figure of Merit for Current
Sources 1142
15.6.3 Higher Output Resistance
Sources 1143
15.6.4 Multiple Output Sources 1144
15.6.5 Current Source Design Examples 1146
Summary 1155
Key Terms 1157
xvi Contents
References 1157
Additional Reading 1157
Problems 1158
C H A P T E R 16
ANALOG INTEGRATED CIRCUITS 1178
16.1 Circuit Element Matching 1180
16.2 Current Mirrors 1181
16.2.1 dc Analysis of the MOS Transistor
Current Mirror 1181
16.2.2 Changing the MOS Mirror Ratio 1183
16.2.3 dc Analysis of the Bipolar Transistor
Current Mirror 1184
16.2.4 Altering the BJT Current Mirror
Ratio 1186
16.2.5 Multiple Current Sources 1188
16.2.6 Buffered Current Mirror 1189
16.2.7 Output Resistance of the Current
Mirrors 1190
16.2.8 Two-Port Model for the Current
Mirror 1191
16.2.9 The Widlar Current Source 1194
16.2.10 The PTAT Voltage 1196
16.2.11 The MOS Version of the Widlar
Source 1197
16.3 High-Output-Resistance Current Mirrors 1198
16.3.1 The Wilson Current Sources 1199
16.3.2 Output Resistance of the Wilson
Source 1201
16.3.3 Cascode Current Sources 1202
16.3.4 Output Resistance of the Cascode
Sources 1202
16.3.5 Current Mirror Summary 1204
16.4 Reference Current Generation 1207
16.4.1 Supply-Independent Biasing 1208
16.4.2 A Supply-Independent MOS Reference
Cell 1211
16.4.3 Variation of Reference Cell Current
with Power Supply Variations 1211
16.5 The Bandgap Reference 1216
16.6 The Current Mirror as an Active Load 1221
16.6.1 CMOS Differential Amplifier with Active
Load 1221
16.6.2 Bipolar Differential Amplifier
with Active Load 1228
16.7 Active Loads in Operational Amplifiers 1232
16.7.1 CMOS Op Amp Voltage Gain 1233
16.7.2 dc Design Considerations 1233
16.7.3 Bipolar Operational Amplifiers 1236
16.7.4 A BJT Amplifier with Improved Voltage
Gain 1237
16.7.5 Input Stage Breakdown 1239
16.8 The _A741 Operational Amplifier 1240
16.8.1 Bias Circuitry 1241
16.8.2 dc Analysis of the 741 Input
Stage 1242
16.8.3 ac Analysis of the 741 Input
Stage 1247
16.8.4 Voltage Gain of the Complete
Amplifier 1248
16.8.5 The 741 Output Stage 1252
16.8.6 Output Resistance 1254
16.8.7 Short Circuit Protection 1254
16.8.8 Summary of the _A741 Operational
Amplifier Characteristics 1255
16.9 The Gilbert Analog Multiplier 1255
Summary 1259
Key Terms 1260
References 1261
Problems 1261
C H A P T E R 17
FREQUENCY RESPONSE 1274
17.1 Amplifier Frequency Response 1275
17.1.1 Low-Frequency Response 1276
17.1.2 Estimating ?L in the Absence
of a Dominant Pole 1277
17.1.3 High-Frequency Response 1280
17.1.4 Estimating ?H in the Absence
of a Dominant Pole 1280
17.2 Direct Determination of the Low-Frequency Poles
and Zeros?The Common-Source
Amplifier 1282
17.3 Estimation of ?L Using the Short-Circuit
Time-Constant Method 1287
17.3.1 Estimate of ?L for the Common-Emitter
Amplifier 1288
17.3.2 Estimate of ?L for the Common-Source
Amplifier 1293
17.3.3 Estimate of ?L for the Common-Base
Amplifier 1293
17.3.4 Estimate of ?L for the Common-Gate
Amplifier 1295
17.3.5 Estimate of ?L for the
Common-Collector Amplifier 1296
17.3.6 Estimate of ?L for the Common-Drain
Amplifier 1297
17.4 Transistor Models at High Frequencies 1297
17.4.1 Frequency-Dependent Hybrid-Pi Model
for the Bipolar Transistor 1297
17.4.2 Modeling C ã and C µ in SPICE 1298
17.4.3 Unity-Gain Frequency fT 1298
17.4.4 High-Frequency Model
for the FET 1302
Contents xvii
17.4.5 Modeling C G S and C G D in SPICE 1303
17.4.6 Channel Length Dependence
of fT 1303
17.4.7 Limitations of the High-Frequency
Models 1305
17.5 Base Resistance in the Hybrid-Pi Model 1306
17.5.1 Effect of Base Resistance on Midband
Amplifiers 1306
17.6 High-Frequency Limitations of Common-Emitter
and Common-Source Amplifiers 1309
17.6.1 Example of Direct High-Frequency
Analysis?The Common-Emitter
Amplifier 1309
17.6.2 Approximate Polynomial
Factorization 1311
17.6.3 Poles of the Common-Emitter
Amplifier?The C T
Approximation 1311
17.6.4 Gain-Bandwidth Product Limitations
of the Common-Emitter Amplifier 1316
17.6.5 Dominant Pole for the Common-Source
Amplifier 1317
17.7 Miller Multiplication 1317
17.7.1 Miller Integrator 1319
17.8 Estimation of ?H for Inverting Amplifiers,
Noninverting Amplifiers, and Followers Using
the Open-Circuit Time-Constant Method 1321
17.8.1 Gain-Bandwidth Trade-Off Using
an Emitter Resistor 1323
17.8.2 Dominant Pole for the Common-Base
Amplifier 1327
17.8.3 Dominant Pole of the Common-Gate
Amplifier 1329
17.8.4 Dominant Pole for the
Common-Collector Amplifier 1330
17.8.5 Dominant Pole for the Common-Drain
Amplifier 1333
17.8.6 Single-Stage Amplifier High-Frequency
Response Summary 1333
17.9 Frequency Response of Multistage
Amplifiers 1334
17.9.1 Differential Amplifier 1334
17.9.2 The Common-Collector/Common-Base
Cascade 1337
17.9.3 High-Frequency Response
of the Cascode Amplifier 1339
17.9.4 Cutoff Frequency for the Current
Mirror 1340
17.9.5 Three-Stage Amplifier Example 1341
17.10 Single-Pole Operational Amplifier
Compensation 1348
17.10.1 Three-Stage Op Amp Analysis 1348
17.10.2 Transmission Zeros in FET
Op Amps 1351
17.10.3 Bipolar Amplifier Compensation 1352
17.10.4 Slew Rate of the Operational
Amplifier 1354
17.10.5 Relationships Between Slew Rate
and Gain-Bandwidth Product 1355
17.11 Tuned Amplifiers 1356
17.11.1 Single-Tuned Amplifier 1356
17.11.2 Use of a Tapped Inductor?The Auto
Transformer 1359
17.11.3 Multiple Tuned Circuits?Synchronous
and Stagger Tuning 1361
17.12 Mixers and Balanced Modulators 1363
17.12.1 A Single-Balanced Mixer 1363
17.12.2 The Gilbert Multiplier as a
Double-Balanced
Mixer/Modulator 1365
17.12.3 Conversion Gain 1367
Summary 1368
Key Terms 1369
References 1370
Problems 1370
C H A P T E R 18
FEEDBACK, STABILITY, AND
OSCILLATORS 1382
18.1 Classic Feedback Systems 1383
18.2 Feedback Amplifier Design Using Two-Port
Network Theory 1384
18.3 Voltage Amplifiers?Series-Shunt
Feedback 1385
18.3.1 Voltage Gain Calculation 1386
18.3.2 Input Resistance 1389
18.3.3 Output Resistance 1389
18.4 Transresistance Amplifiers?Shunt-Shunt
Feedback 1394
18.4.1 Transresistance Analysis 1394
18.4.2 Input Resistance 1397
18.4.3 Output Resistance 1398
18.5 Current Amplifiers?Shunt-Series
Feedback 1403
18.5.1 Current Gain Calculation 1403
18.5.2 Input Resistance 1404
18.5.3 Output Resistance 1405
18.6 Transconductance Amplifiers?Series-Series
Feedback 1407
18.6.1 Transconductance Analysis 1407
18.6.2 Input and Output Resistances 1409
18.7 Common Errors in Applying Two-Port Feedback
Theory 1409
18.8 Finding the Loop Gain 1419
18.8.1 Direct Calculation of the Loop
Gain 1419
xviii Contents
18.8.2 Finding the Loop Gain Using Successive
Voltage and Current Injection 1420
18.8.3 Simplifications 1424
18.9 Blackman?s Theorem to the Rescue 1427
18.10 Using Feedback to Control Frequency
Response 1434
18.11 Stability of Feedback Amplifiers 1436
18.11.1 The Nyquist Plot 1436
18.11.2 First-Order Systems 1436
18.11.3 Second-Order Systems and Phase
Margin 1438
18.11.4 Third-Order Systems and Gain
Margin 1439
18.11.5 Determining Stability from
the Bode Plot 1440
18.12 Oscillators 1449
18.12.1 The Barkhausen Criteria
for Oscillation 1449
18.12.2 Oscillators Employing
Frequency-Selective RC
Networks 1450
18.12.3 LC Oscillators 1454
18.12.4 Crystal Oscillators 1458
Summary 1463
Key Terms 1464
References 1464
Problems 1465
A P P E N D I X E S
A Standard Discrete Component Values 1476
B Solid-State Device Models and SPICE
Simulation Parameters 1480
Index 1487

Library of Congress Subject Headings for this publication:

Integrated circuits -- Design and construction.
Semiconductors -- Design and construction.
Electronic circuit design.