Table of contents for Digital design : basic concepts and principles / by Mohammad A. Karim and Xinghao Chen.

Bibliographic record and links to related information available from the Library of Congress catalog.

Note: Contents data are machine generated based on pre-publication provided by the publisher. Contents may have variations from the printed book or be incomplete or contain other coding.


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CONTENTS
Preface
1.	Data Type and Representations
1.1.	Introduction 
1.2.	Positional Number Systems
1.3.	Number System Conversion
1.4.	Negative Numbers
1.5.	Binary Arithmetic
1.6.	Unconventional Number System 
1.7.	Binary Codes
1.8.	Error Detecting and Correcting Codes
1.9.	CAD System
1.10.	Summary
Problems
2.	Boolean Algebra
2.1.	Introduction
2.2.	Logic Operations
2.3.	Logic Functions from Truth Tables
2.4.	Boolean Algebra
2.5.	Summary
Problems
3.	Minimization of Logic Functions
3.1.	Introduction
3.2.	Karnaugh Map
3.3.	Incompletely Specified Functions in K-Map
3.4.	K-Maps for Product-of-sum Form of Functions
3.5.	Map-entered Variables
3.6.	Hazards
3.7.	Single-output Q-M Tabular Reduction
3.8.	Multiple-output Q-M Tabular reduction
3.9.	Summary 
Problems			
4.	Logic Function Implementation
4.1.	Introduction
4.2.	Functionally Complete Operation Sets
4.3.	NAND-only and NOR-only Implementations
4.4.	Function Implementation Using XOR and XNOR Logic
4.5.	Circuit Implementation Using Gate Arrays
4.6.	Logic Function Implementation Using Multiplexers
4.7.	Logic Function Implementation Using Demultiplexers and Decoders
4.8.	Logic Function Implementation Using ROM
4.9.	Logic Function Implementation Using PLD
4.10.	Logic Function Implementation Using Threshold Logic
4.11.	Logic Function Implementation Using Transmission Gates
4.12.	Summary
Problems
5.	Introduction to VHDL
5.1.	VHDL Programming Environment
5.2.	Structural VHDL
5.3.	Functional VHDL 
5.4.	Behavioral VHDL
5.5.	Hierarchical VHDL
5.6.	Logic Circuit Synthesis with Xilinx WebPACK ISE Project Navigator
5.7.	Simulation of Timing Characteristics
5.8.	Logic Circuit Implementation with FPGA Device
5.9.	Summary
	Problems
6.	Design of Modular Combinatorial Components
6.1.	Introduction
6.2.	Special-purpose Decoders and Encoders
6.3.	Code Converters
6.4.	Error-detecting and Error-correcting Circuits
6.5.	Binary Arithmetic
6.6.	Binary Subtraction
6.7.	High-Speed Addition
6.8.	BCD Arithmetic
6.9.	Comparators
6.10.	Combinatorial Circuit Design Using VHDL
6.11.	Arithmetic Logic Unit
6.12.	ALU Design Using VHDL
6.13.	Summary
Problems
7.	Sequential Logic Elements
7.1.	Introduction
7.2.	Latches
7.3.	Set-Reset Flip-Flop
7.4.	JK Flip-Flop
7.5.	Master-Slave Flip-Flop
7.6.	Edge-Triggered Flip-Flop
7.7.	Delay and Trigger Flip-Flop
7.8.	Monostable Flip-Flop
7.9.	Design of Sequential Elements Using VHDL
7.10.	Sequential Circuits
7.11.	Summary
Problems
8.	Synchronous Sequential Circuits
8.1.	Introduction
8.2.	Formalism
8.3.	Mealy and Moore Models
8.4.	Analysis of Sequential Circuits
8.5.	Equivalent States
8.6.	Incompletely Specified Sequential Circuits
8.7.	State Assignments
8.8.	Design Algorithm
8.9.	Synchronous Sequential Circuit Implementation Using VHDL
8.10.	Summary	
Problems
9.	Modular Sequential Components
9.1.	Introduction 
9.2.	Synchronous Counters 
9.3.	Registers
9.4.	Shift Registers as Counters
9.5.	Counter and Register Applications
9.6.	RTL
9.7.	Registers and Counters Using VHDL
9.8.	Summary
Problems
10.	Sequential Arithmetic
10.1.	Introduction
10.2.	Serial Adder/Subtracter
10.3.	Serial-Parallel Multiplication
10.4.	Fast Multiplication
10.5.	Implementation of Sequential Arithmetic in VHDL
10.6.	Summary
Problems
11.	Asynchronous Sequential Circuits. 
11.1.	Introduction
11.2.	Pulse Mode Circuits
11.3.	Fundamental Mode Circuits
11.4.	Cycles, Races, and Hazards
11.5.	Fundamental Mode Outputs 
11.6.	Summary
Problems
12.	Introduction to Testability
12.1.	Introduction
12.2.	Controllability and Observability
12.3.	Deterministic Testability versus Ransom Testability
12.4.	Test of Integrated Circuits
12.5.	Fault Models
12.6.	Test Sets and Test Generation
12.7.	Topology-based Testability Analysis
12.8.	Simulation-based Testability Analysis
12.9.	Fault Analysis and Fault-based Testability Analysis
12.10.	Testability Matrices
12.11.	Design-for-Testability
12.12.	Summary
	 Problems			
	

Library of Congress Subject Headings for this publication:

Digital electronics.
Logic design.