Table of contents for Computer organization, design, and architecture / Sajjan G. Shiva.

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Table of Contents
1	Introduction
1.1	COMPUTER SYSTEM ORGANIZATION
1.1.1	Hardware
1.1.2	Software
1.1.3	System
1.2	COMPUTER EVOLUTION
1.2.1	Von Neumann Model
1.2.2	Generations of Computer Technology
1.2.3	Moore¿s Law
1.3	ORGANIZATION VS. DESIGN VS. ARCHITECTURE
1.4	PERFORMANCE EVALUATION
1.4.1	Benchmarks
1.5	SUMMARY
REFERENCES
PROBLEMS
2	Number Systems and Codes
2.1	NUMBER SYSTEMS
2.1.1	Binary System
2.1.2	Octal System
2.1.3	Hexadecimal System
2.2	CONVERSION
2.2.1	Radix Divide Technique
2.2.2	Radix Multiply Technique
2.2.3	Base 2k Conversion
2.3	ARITHMETIC
2.3.1	Binary Arithmetic
2.3.2	Octal Arithmetic
2.3.3	Hexadecimal Arithmetic
2.4	SIGN-MAGNITUDE SYSTEM
2.5	COMPLEMENT NUMBER SYSTEM
2.5.1	Twos Complement Addition
2.5.2	Ones Complement Addition
2.5.3	Shifting Revisited
2.5.4	Comparison of Complement Systems
2.6	FLOATING-POINT NUMBERS
2.6.1	The IEEE standard
2.7	BINARY CODES
2.7.1	Weighted Codes
2.7.2	Nonweighted Codes
2.7.3	Error Detection Codes
2.7.4	Alphanumeric Codes
2.8	DATA STORAGE AND REGISTER TRANSFER
2.9	REPRESENTATION OF NUMBERS, ARRAYS AND RECORDS
2.10	SUMMARY
REFERENCES
PROBLEMS
3	Combinational Logic
3.1	BASIC OPERATIONS AND TERMINOLOGY
3.1.1	Evaluation of Expressions
3.1.2	Truth Tables
3.1.3	Functions and Their Representation
3.1.4	Canonical Forms
3.2	BOOLEAN ALGEBRA (SWITCHING ALGEBRA)
3.3	MINIMIZATION OF BOOLEAN FUNCTIONS
3.3.1	Venn Diagrams
3.3.2	Karnaugh Maps
3.3.3	The Quine-McCluskey Procedure
3.4	PRIMITIVE HARDWARE BLOCKS
3.5	FUNCTIONAL ANALYSIS OF COMBINATIONAL CIRCUITS
3.6	SYNTHESIS OF COMBINATIONAL CIRCUITS
3.6.1	AND¿OR Circuits
3.6.2	OR¿AND Circuits
3.6.3	NAND¿NAND and NOR¿NOR Circuits
3.7	SOME POPULAR COMBINATIONAL CIRCUITS
3.7.1	Adders
3.7.2	Decoders
3.7.3	Code Converters
3.7.4	Encoders
3.7.5	Multiplexers
3.7.6	Demultiplexers
3.8	INTEGRATED CIRCUITS
3.8.1	Positive and Negative Logic
3.8.2	Signal Inversion
3.8.3	Other Characteristics
3.8.4	Special Outputs
3.8.5	Designing with ICs
3.9	LOADING AND TIMING
3.10	SUMMARY
REFERENCES
PROBLEMS
4	Synchronous Sequential Circuits
4.1	FLIP-FLOPS
4.1.1	Set-Reset (SR) Flip-Flop
4.1.2	D Flip-Flops
4.1.3	JK Flip-Flops
4.1.4	T Flip-Flops
4.1.5	Characteristic and Excitation Tables
4.2	TIMING CHARACTERISTICS OF FLIP-FLOPS
4.2.1	Master Slave Flip-Flops
4.2.2	Edge-Triggered Flip-Flops
4.3	FLIP-FLOP ICS
4.4	ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
4.5	DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS
4.6	REGISTERS
4.7	REGISTER TRANSFER LOGIC
4.8	REGISTER TRANSFER SCHEMES
4.8.1	Point-to-Point Transfer
4.8.2	Bus Transfer
4.9	REGISTER TRANSFER LANGUAGES
4.10	DESIGNING SEQUENTIAL CIRCUITS WITH INTEGRATED CIRCUITS
4.11	PROGRAMMABLE LOGIC
4.11.1	Circuit Implementation Modes and Devices
4.11.2	Programmable Logic Arrays (PLAs)
4.11.3	Programmable Array Logic (PAL)
4.11.4	Gate Arrays (GA)
4.12	SUMMARY
REFERENCES
PROBLEMS
5	A Simple Computer: Organization and Programming
5.1	A SIMPLE COMPUTER
5.1.1	Data Format
5.1.2	Instruction Format
5.1.3	Instruction Set
5.1.4	Addressing Modes
5.1.5	Other Addressing Modes
5.1.6	Addressing Limitations
5.1.7	Machine Language Programming
5.2	ASC ASSEMBLER
5.2.1	Assembly Process
5.3	PROGRAM LOADING
5.4	SUBROUTINES
5.5	MACROS
5.6	LINKERS AND LOADERS
5.6.1	Dynamic Linking
5.7	SUMMARY
REFERENCES
PROBLEMS
6	A Simple Computer: Hardware Design
6.1	PROGRAM EXECUTION
6.1.1	Instruction Fetch
6.1.2	Instruction Execution
6.2	DATA, INSTRUCTION, AND ADDRESS FLOW
6.2.1	Fetch Phase
6.2.2	Address Calculations
6.2.3	Execution Phase
6.3	BUS STRUCTURE
6.4	ARITHMETIC AND LOGIC UNIT
6.5	INPUT/OUTPUT
6.6	CONTROL UNIT
6.6.1	Types of Control Units
6.6.2	Hardwired Control Unit for ASC
6.6.3	Memory versus Processor Speed
6.6.4	Machine Cycles
6.6.5	One-address Instructions
6.6.6	Zero-Address Instructions
6.6.7	Input/Output Instructions
6.7	CONSOLE
6.8	MICROPROGRAMMED CONTROL UNIT
6.8.1	MCU for ASC
6.9	SUMMARY
REFERENCES
PROBLEMS
7	Input/Output
7.1	GENERAL I/O MODEL
7.2	THE I/O FUNCTION
7.2.1	Timing
7.2.2	Control
7.2.3	Data Conversion
7.2.4	Error Detection and Correction
7.3	INTERRUPTS
7.3.1	Interrupt Mechanism for ASC
7.3.2	Multiple Interrupts
7.3.3	Polling
7.3.4	Vectored Interrupts
7.3.5	Types of Interrupt Structures
7.4	DIRECT MEMORY ACCESS
7.5	BUS ARCHITECTURE
7.5.1	Bus Control (Arbitration)
7.5.2	Bus Standards
7.6	CHANNELS
7.7	I/O PROCESSORS (IOP)
7.7.1	IOP Organization
7.8	SERIAL I/O
7.9	COMMON I/O DEVICES
7.9.1	Terminals
7.9.2	Mouse
7.9.3	Printers
7.9.4	Scanners
7.9.5	A/D and D/A Converters
7.9.6	Tapes and Disks
7.10	EXAMPLES
7.10.1	Motorola 68000
7.10.2	Intel 21285
7.10.3	Control Data 6600
7.11	SUMMARY
REFERENCES
PROBLEMS
8	Processor and Instruction Set Architectures
8.1	TYPES OF COMPUTER SYSTEMS
8.2	OPERAND (DATA) TYPES AND FORMATS
8.2.1	Fixed Point
8.2.2	Decimal Data
8.2.3	Character Strings
8.2.4	Floating-point Numbers
8.2.5	Endien
8.2.6	Register vs. memory storage
8.3	REGISTERS
8.4	INSTRUCTION SET
8.4.1	Instruction types
8.4.2	Instruction Length
8.4.3	Opcode Selection
8.4.4	Instruction Formats
8.5	ADDRESSING MODES
8.5.1	Immediate Addressing
8.5.2	Paged Addressing
8.5.3	Base-register Addressing
8.5.4	Relative Addressing
8.5.5	Implied (Implicit) Addressing
8.6	INSTRUCTION SET ORTHOGANALITY
8.7	RISC VS. CISC
8.8	EXAMPLE SYSTEMS
8.8.1	Intel 8080
8.8.2	Intel 8086
8.8.3	Intel Pentium
8.9	SUMMARY
REFERENCES
PROBLEMS
9	Memory and Storage
9.1	TYPES OF MEMORY
9.1.1	Random-access Memory
9.1.2	Content-addressable Memory
9.1.3	Sequential-access Memory
9.1.4	Direct-access Memory
9.2	MEMORY SYSTEM PARAMETERS
9.3	MEMORY HIERARCHY
9.4	MEMORY DEVICES AND ORGANIZATIONS
9.4.1	Random-access Memory Devices
9.4.2	Associative Memory
9.4.3	Sequential-access Memory Devices
9.4.4	Direct-access Storage Devices
9.5	MEMORY SYSTEM DESIGN USING ICS
9.6	SPEED ENHANCEMENT
9.6.1	Banking
9.6.2	Interleaving
9.6.3	Multiport Memories
9.6.4	Wider Word Fetch
9.6.5	Instruction Buffer
9.6.6	Cache Memory
9.7	SIZE ENHANCEMENT
9.8	ADDRESS EXTENSION
9.9	EXAMPLE SYSTEMS
9.9.1	Memory Management in Intel Processors
9.9.2	Motorola 68020 Memory Management
9.9.3	Sun-3 System Memory Management
9.10	SUMMARY
REFERENCES
PROBLEMS
10	Arithmetic/Logic Unit Enhancement
10.1	LOGICAL AND FIXED-POINT BINARY OPERATIONS
10.1.1	Logical Operations
10.1.2	Addition and Subtraction
10.1.3	Multiplication
10.1.4	Division
10.1.5	Stack-based ALU
10.2	DECIMAL ARITHMETIC
10.3	PIPELINING
10.4	ALU WITH MULTIPLE FUNCTIONAL UNITS
10.5	EXAMPLE SYSTEMS
10.5.1	A Multifunction ALU IC (74181)
10.5.2	Texas Instruments¿ MSP 430 Hardware Multiplier
10.5.3	Motorola 68881 Coprocessor
10.5.4	Control Data 6600
10.5.5	Architecture of the Cray Series
10.6	SUMMARY
REFERENCES
PROBLEMS
11	Control Unit Enhancement
11.1	SPEED ENHANCEMENT
11.1.1	Instruction Cycle Speedup
11.1.2	Instruction Execution Overlap
11.1.3	Parallel Instruction Execution
11.1.4	Instruction Buffer and Cache
11.2	HARDWIRED VS. MICROPROGRAMMED CONTROL UNITS
11.3	PIPELINE PERFORMANCE ISSUES
11.3.1	Data Interlocks
11.3.2	Conditional branches
11.3.3	Interrupts
11.3.4	Instruction Deferral
11.4	EXAMPLE SYSTEMS
11.4.1	Sun Microsystem¿s Niagara microprocessor (Geppert, 2005)
11.4.2	Motorola MC88100/88200
11.4.3	MIPS R10000 Architecture
11.4.4	Intel Corporation¿s Itanium
11.5	SUMMARY
REFERENCES
PROBLEMS
12	Advanced Architectures
12.1	MISD
12.2	SIMD
12.2.1	Interconnection networks for SIMD architectures
12.3	MIMD
12.3.1	MIMD Organization
12.3.2	Interconnection Networks for MIMD Architectures
12.4	CACHE COHERENCE
12.5	DATA-FLOW ARCHITECTURES
12.6	SYSTOLIC ARCHITECTURES
12.7	EXAMPLE SYSTEMS
12.7.1	Cray XT4
12.8	SUMMARY
REFERENCES
PROBLEMS
13	Embedded Systems
13.1	CHARACTERISTICS
13.2	SOFTWARE ARCHITECTURES
13.2.1	Simple control loop (Round Robin)
13.2.2	Interrupt controlled loop (Round Robin with Interrupts)
13.2.3	RTOS-based Architectures
13.3	OPERATING SYSTEM (OS)
13.3.1	Multitasking Vs Concurrency
13.3.2	Process handling
13.3.3	Synchronization Mechanisms
13.3.4	Scheduling
13.3.5	Real-Time Operating Systems (RTOS)
13.4	EXAMPLE SYSTEMS
13.4.1	The 8051 Family of Microcontrollers
DS89C450 Ultra-High-Speed Flash Microcontroller
13.4.2	ARM (Advanced RISC Machine) Microprocessor:
13.5	SUMMARY
REFERENCES
PROBLEMS
14	COMPUTER NETWORKS AND DISTRIBUTED PROCESSING
14.1	COMPUTER NETWORKS
14.1.1	Network Architecture
14.1.2	Network Reference Models
14.1.3	Network Standardization
14.1.4	Computer Network Types
14.1.5	Internet and WWW
14.2	DISTRIBUTED PROCESSING
14.2.1	Processes and Threads
14.2.2	Remote procedure call
14.2.3	Process Synchronization and Mutual Exclusion
14.2.4	Election algorithms
14.3	GRID COMPUTING
14.3.1	OGSA
14.4	SUMMARY
REFERENCES
PROBLEMS
15	Performance Evaluation
15.1	PERFORMANCE MEASURES
15.2	COST FACTOR
15.3	BENCHMARKS
15.4	CODE OPTIMIZATION
15.5	SUMMARY
REFERENCES
PROBLEMS
Appendix A
Details of Representative Integrated Circuits
A.1	GATES, DECODERS AND OTHER ICS USEFUL IN COMBINATIONAL CIRCUIT DESIGN
A.2	FLIP-FLOPS, REGISTERS AND OTHER ICS USEFUL IN SEQUENTIAL CIRCUIT DESIGN
A.3	MEMORY ICS
Signetics 74S189
Intel 2114
Texas Instruments TMS4116
INTEL 8202A Dynamic RAM Controller
REFERENCES
Appendix B
Stack Implementation

Library of Congress Subject Headings for this publication:

Computer engineering.
Computer architecture.