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Contents (page numbers will change) CHAPTER 1 Number Systems and Codes 2 Outline 2 Objectives 3 Introduction 3 1-1 Digital Versus Analog 4 1-2 Digital Representations of Analog Quantities 5 1-3 Decimal Numbering System (Base 10) 7 1-4 Binary Numbering System (Base 2) 8 1-5 Decimal-to-Binary Conversion 10 1-6 Octal Numbering System (Base 8) 12 1-7 Octal Conversions 12 1-8 Hexadecimal Numbering System (Base 16) 14 1-9 Hexadecimal Conversions 15 1-10 Binary-Coded-Decimal System 17 1-11 Comparison of Numbering Systems 18 1-12 The ASCII Code 18 1-13 Applications of the Numbering Systems 20 Summary 23 Glossary 23 Problems 24 Schematic Interpretation Problems 26 Electronics Workbench(r)/Multisim(r) Exercises 26 Answers to Review Questions 27 CHAPTER 2 Digital Electronic Signals and Switches 28 Outline 28 Objectives 29 Introduction 29 2-1 Digital Signals 30 2-2 Clock Waveform Timing 30 2-3 Serial Representation 32 2-4 Parallel Representation 33 2-5 Switches in Electronic Circuits 36 2-6 A Relay as a Switch 37 2-7 A Diode as a Switch 40 2-8 A Transistor as a Switch 43 2-9 The TTL Integrated Circuit 47 2-10 The CMOS Integrated Circuit 50 2-11 Surface-Mount Devices 51 Summary 52 Glossary 53 Problems 54 Schematic Interpretation Problems 57 Electronics Workbench(r)/Multisim(r) Exercises 57 Answers to Review Questions 58 CHAPTER 3 Basic Logic Gates 60 Outline 60 Objectives 61 Introduction 61 3-1 The AND Gate 62 3-2 The OR Gate 64 3-3 Timing Analysis 66 3-4 Enable and Disable Functions 68 3-5 Using IC Logic Gates 70 3-6 Introduction to Troubleshooting Techniques 71 3-7 The Inverter 77 3-8 The NAND Gate 77 3-9 The NOR Gate 80 3-10 Logic Gate Waveform Generation 82 3-11 Using IC Logic Gates 88 3-12 Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols 90 Summary 93 Glossary 93 Problems 94 Schematic Interpretation Problems 105 Electronics Workbench(r)/Multisim(r) Exercises 106 Answers to Review Questions 108 CHAPTER 4 Programmable Logic Devices: Altera and Xilinx CPLDs and FPGAs 110 Outline 110 Objectives 111 Introduction 111 4-1 PLD Design Flow 112 4-2 PLD Architecture 115 4-3 Using PLDs to Solve Basic Logic Designs 118 Summary 126 Glossary 126 Problems 127 CPLD Problems 129 CHAPTER 5 Boolean Algebra and Reduction Techniques 130 Outline 130 Objectives 131 Introduction 131 5-1 Combinational Logic 132 5-2 Boolean Algebra Laws and Rules 134 5-3 Simplification of Combinational Logic Circuits Using Boolean Algebra 139 5-4 De Morgan's Theorem 143 5-5 The Universal Capability of NAND and NOR Gates 154 5-6 AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions 159 5-7 Karnaugh Mapping 163 5-8 System Design Applications 170 5-9 CPLD Design Applications 172 Summary 177 Glossary 177 Problems 178 Schematic Interpretation Problems 189 Electronics Workbench(r)/Multisim(r) Exercises 190 CPLD Problems 193 Answers to Review Questions 195 CHAPTER 6 Exclusive-OR and Exclusive-NOR Gates 196 Outline 196 Objectives 197 Introduction 197 6-1 The Exclusive-OR Gate 198 6-2 The Exclusive-NOR Gate 199 6-3 Parity Generator/Checker 202 6-4 System Design Applications 205 6-5 CPLD Design Applications 208 ummary 211 Glossary 211 Problems 211 Schematic Interpretation Problems 214 Electronics Workbench(r)/Multisim(r) Exercises 215 CPLD Problems 216 Answers to Review Questions 217 CHAPTER 7 Arithmetic Operations and Circuits 218 Outline 218 Objectives 219 Introduction 219 7-1 Binary Arithmetic 220 7-2 Two's-Complement Representation 226 7-3 Two's-Complement Arithmetic 229 7-4 Hexadecimal Arithmetic 230 7-5 BCD Arithmetic 233 7-6 Arithmetic Circuits 235 7-7 Four-Bit Full-Adder ICs 239 7-8 System Design Applications 242 7-9 Arithmetic/Logic Units 245 7-10 CPLD Design Applications 248 Summary 251 Glossary 251 Problems 253 Schematic Interpretation Problems 257 Electronics Workbench(r)/Multisim(r) Exercises 257 CPLD Problems 258 Answers to Review Questions 259 CHAPTER 8 Code Converters, Multiplexers, and Demultiplexers 260 Outline 260 Objectives 261 Introduction 261 8-1 Comparators 262 8-2 Decoding 264 8-3 Encoding 272 8-4 Code Converters 277 8-5 Multiplexers 285 8-6 Demultiplexers 290 8-7 System Design Applications 294 8-8 CPLD Design Applications 300 Summary 303 Glossary 303 Problems 304 Schematic Interpretation Problems 311 Electronics Workbench(r)/Multisim(r) Exercises 311 CPLD Problems 314 Answers to Review Questions 315 CHAPTER 9 Logic Families and Their Characteristics 316 Outline 316 Objectives 317 Introduction 317 9-1 The TTL Family 318 9-2 TTL Voltage and Current Ratings 320 9-3 Other TTL Considerations 329 9-4 Improved TTL Series 334 9-5 The CMOS Family 336 9-6 Emitter-Coupled Logic 341 9-7 Comparing Logic Families 343 9-8 Interfacing Logic Families 344 Summary 351 Glossary 352 Problems 353 Schematic Interpretation Problems 357 Electronics Workbench(r)/Multisim(r) Exercises 358 Answers to Review Questions 358 CHAPTER 10 Flip-Flops and Registers 360 Outline 360 Objectives 361 Introduction 361 10-1 S-R Flip-Flop 362 10-2 Gated S-R Flip-Flop 366 10-3 Gated D Flip-Flop 368 10-4 Integrated-Circuit D Latch (7475) 368 10-5 Integrated-Circuit D Flip-Flop (7474) 370 10-6 Master-Slave J-K Flip-Flop 374 10-7 Edge-Triggered J-K Flip-Flop 378 10-8 Integrated-Circuit J-K Flip-Flop (7476, 74LS76) 380 10-9 Using an Octal D Flip-Flop in a Microcontroller Application 387 Summary 389 Glossary 389 Problems 391 Schematic Interpretation Problems 398 Electronics Workbench(r)/Multisim(r) Exercises 399 CPLD Problems 400 Answers to Review Questions 401 CHAPTER 11 Practical Considerations for Digital Design 402 Outline 402 Objectives 403 Introduction 403 11-1 Flip-Flop Time Parameters 404 11-2 Automatic Reset 419 11-3 Schmitt Trigger ICs 421 11-4 Switch Debouncing 426 11-5 Sizing Pull-Up Resistors 429 11-6 Practical Input and Output Considerations 430 Summary 436 Glossary 436 Problems 438 Schematic Interpretation Problems 443 Electronics Workbench(r)/Multisim(r) Exercises 444 Answers to Review Questions 444 CHAPTER 12 Counter Circuits and Applications 446 Outline 446 Objectives 447 Introduction 447 12-1 Analysis of Sequential Circuits 448 12-2 Ripple Counters 452 12-3 Design of Divide-by-N Counters 457 12-4 Ripple Counter ICs 463 12-5 System Design Applications 469 12-6 Seven-Segment LED Display Decoders 475 12-7 Synchronous Counters 482 12-8 Synchronous Up/Down-Counter ICs 486 12-9 Applications of Synchronous Counter ICs 494 12-10 CPLD Design Applications 498 Summary 499 Glossary 500 Problems 501 Schematic Interpretation Problems 507 Electronics Workbench(r)/Multisim(r) Exercises 508 CPLD Problems 509 Answers to Review Questions 510 CHAPTER 13 Shift Registers 512 Outline 512 Objectives 513 Introduction 513 13-1 Shift Register Basics 514 13-2 Parallel-to-Serial Conversion 516 13-3 Recirculating Register 516 13-4 Serial-to-Parallel Conversion 518 13-5 Ring Shift Counter and Johnson Shift Counter 518 13-6 Shift Register ICs 522 13-7 System Design Applications for Shift Registers 530 13-8 Driving a Stepper Motor with a Shift Register 535 13-9 Three-State Buffers, Latches, and Transceivers 538 13-10 CPLD Design Applications 543 Summary 544 Glossary 545 Problems 547 Schematic Interpretation Problems 552 Electronics Workbench(r)/Multisim(r) Exercises 553 CPLD Problems 554 Answers to Review Questions 555 CHAPTER 14 Multivibrators and the 555 Timer 556 Outline 556 Objectives 557 Introduction 557 14-1 Multivibrators 558 14-2 Capacitor Charge and Discharge Rates 558 14-3 Astable Multivibrators 562 14-4 Monostable Multivibrators 564 14-5 Integrated-Circuit Monostable Multivibrators 567 14-6 Retriggerable Monostable Multivibrators 571 14-7 Astable Operation of the 555 IC Timer 574 14-8 Monostable Operation of the 555 IC Timer 579 14-9 Crystal Oscillators 582 Summary 584 Glossary 584 Problems 585 Schematic Interpretation Problems 588 Electronics Workbench(r)/Multisim(r) Exercises 589 Answers to Review Questions 590 CHAPTER 15 Interfacing to the Analog World 592 Outline 592 Objectives 593 Introduction 593 15-1 Digital and Analog Representations 594 15-2 Operational Amplifier Basics 595 15-3 Binary-Weighted D/A Converters 596 15-4 R/2R Ladder D/A Converters 597 15-5 Integrated-Circuit D/A Converters 599 15-6 Integrated-Circuit Data Converter Specifications 602 15-7 Parallel-Encoded A/D Converters 603 15-8 Counter-Ramp A/D Converters 605 15-9 Successive-Approximation A/D Conversion 606 15-10 Integrated-Circuit A/D Converters 608 15-11 Data Acquisition System Application 613 15-12 Transducers and Signal Conditioning 616 Summary 620 Glossary 621 Problems 623 Schematic Interpretation Problems 626 Electronics Workbench(r)/Multisim(r) Exercises 626 Answers to Review Questions 627 CHAPTER 16 Semiconductor, Magnetic, and Optical Memory 628 Outline 628 Objectives 629 Introduction 629 16-1 Memory Concepts 630 16-2 Static RAMs 633 16-3 Dynamic RAMs 641 16-4 Read-Only Memories 648 16-5 Memory Expansion and Address Decoding Applications 655 16-6 Magnetic and Optical Storage 660 Summary 664 Glossary 665 Problems 666 Schematic Interpretation Problems 669 Electronics Workbench(r)/Multisim(r) Exercises 670 Answers to Review Questions 670 CHAPTER 17 Microprocessor Fundamentals 672 Outline 672 Objectives 673 Introduction 673 17-1 Introduction to System Components and Buses 674 17-2 Software Control of Microprocessor Systems 677 17-3 Internal Architecture of a Microprocessor 677 17-4 Instruction Execution Within a Microprocessor 679 17-5 Hardware Requirements for Basic I/O Programming 682 17-6 Writing Assembly Language and Machine Language Programs 684 17-7 Survey of Microprocessors and Manufacturers 687 Summary of Instructions 688 Summary 688 Glossary 689 Problems 691 Schematic Interpretation Problems 693 Electronics Workbench(r)/Multisim(r) Exercises 693 Answers to Review Questions 694 CHAPTER 18 The 8051 Microcontroller Outline Objectives Introduction 18-1 The 8051 Family of Microcontrollers 18-2 8051 Architecture 18-3 Interfacing to External Memory 18-4 The 8051 Instruction Set 18-5 8051 Applications 18-6 Data Acquisition and Control System Application Summary Glossary Problems Schematic Interpretation Problem APPENDIX A www sites 695 APPENDIX B Manufacturers' Data Sheets 697 APPENDIX C -Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation) 756 APPENDIX D Answers to Odd-Numbered Problems 761 APPENDIX E -CPLD Software Tutorials 782 E-1 Altera Max1Plus II 782E-2 Xilinx Foundation 796 APPENDIX F Review of Basic Electricity Principles 818 APPENDIX G Schematic Diagrams for Chapter-End Problems 828 APPENDIX H 8051 Instruction Set Summary INDEX 837 SUPPLEMENTARY INDEX OF ICs 843
Library of Congress Subject Headings for this publication: Digital electronics