Table of contents for Low power networks-on-chip / Cristina Silvano, Marcello Lajolo, Gianluca Palermo, editors.

Bibliographic record and links to related information available from the Library of Congress catalog

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Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.

Library of Congress subject headings for this publication:
Networks on a chip.
Low voltage integrated circuits.