Table of contents for Logic synthesis and verification algorithms / Gary Hachtel, Fabio Somenzi.
Bibliographic record and links to related information available from the Library of Congress catalog
Information from electronic data provided by the publisher. May be incomplete or contain other coding.
I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.
Library of Congress subject headings for this publication: